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path: root/llvm/lib/Target/AArch64/AArch64CallLowering.cpp
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* [NFC] Fix trivial typos in commentsJames Henderson2020-01-061-1/+1
* When lowering calls and tail calls in AArch64, the register mask andEric Christopher2019-11-061-3/+3
* [globalisel] Rename G_GEP to G_PTR_ADDDaniel Sanders2019-11-051-1/+1
* [GISel][CallLowering] Make isIncomingArgumentHandler a pure virtual methodQuentin Colombet2019-10-181-0/+2
* [AArch64][GlobalISel] Support lowering variadic musttail callsJessica Paquette2019-09-301-11/+69
* [AArch64][GlobalISel] Choose CCAssignFns per-argument for tail call loweringJessica Paquette2019-09-251-17/+33
* [AArch64][GlobalISel] Support lowering musttail callsJessica Paquette2019-09-181-10/+24
* [AArch64][GlobalISel] Support -tailcalloptJessica Paquette2019-09-171-23/+105
* AArch64CallLowering::lowerCall(): fix build by not passing InArgs into lowerT...Roman Lebedev2019-09-171-1/+1
* [AArch64][GlobalISel][NFC] Refactor tail call lowering codeJessica Paquette2019-09-171-31/+71
* [AArch64][GlobalISel] Tail call memory intrinsicsJessica Paquette2019-09-131-1/+3
* [AArch64][GlobalISel] Add support for sibcalling callees with varargsJessica Paquette2019-09-131-6/+19
* [AArch64][GlobalISel] Support tail calling with swiftself parametersJessica Paquette2019-09-121-5/+32
* [AArch64][GlobalISel] Support sibling calls with outgoing argumentsJessica Paquette2019-09-121-21/+96
* AArch64: support arm64_32, an ILP32 slice for watchOS.Tim Northover2019-09-121-4/+6
* [GlobalISel][AArch64] Check caller for swifterror params in tailcall eligibilityJessica Paquette2019-09-111-3/+7
* [GlobalISel] When a tail call is emitted in a block, stop translating itJessica Paquette2019-09-101-11/+0
* [AArch64][GlobalISel] Support sibling calls with mismatched calling conventionsJessica Paquette2019-09-101-15/+46
* [GlobalISel][AArch64] Handle tail calls with non-void return typesJessica Paquette2019-09-091-15/+9
* [AArch64][GlobalISel] Always fall back on tail calls with -tailcalloptJessica Paquette2019-09-061-0/+6
* Recommit "[AArch64][GlobalISel] Teach AArch64CallLowering to handle basic sib...Jessica Paquette2019-09-051-7/+186
* Revert rL370996 from llvm/trunk: [AArch64][GlobalISel] Teach AArch64CallLower...Simon Pilgrim2019-09-051-169/+7
* [AArch64][GlobalISel] Teach AArch64CallLowering to handle basic sibling callsJessica Paquette2019-09-041-7/+169
* [GlobalISel][CallLowering] Add support for splitting types according to calli...Amara Emerson2019-09-031-7/+8
* [AArch64][GlobalISel] Fall back when translating musttail callsJessica Paquette2019-08-281-0/+5
* GlobalISel: pack various parameters for lowerCall into a struct.Tim Northover2019-08-091-19/+15
* [GlobalISel][CallLowering] Rename isArgumentHandler() -> isIncomingArgumentHa...Amara Emerson2019-08-051-1/+1
* GlobalISel: support swiftself attributeTim Northover2019-08-021-0/+1
* [GISel] Pass MD_callees metadata down in call lowering.Mark Lacey2019-07-311-1/+2
* [AArch64 GlobalISel] Cleanup CallLowering. NFCIDiana Picus2019-06-271-45/+11
* [GlobalISel] Accept multiple vregs for lowerCall's argsDiana Picus2019-06-271-2/+1
* [GlobalISel] Accept multiple vregs for lowerCall's resultDiana Picus2019-06-271-9/+3
* [GlobalISel] Accept multiple vregs in lowerFormalArgsDiana Picus2019-06-271-19/+24
* [GlobalISel] Allow multiple VRegs in ArgInfo. NFCDiana Picus2019-06-271-7/+10
* GlobalISel: Remove unsigned variant of SrcOpMatt Arsenault2019-06-241-16/+16
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-5/+5
* GlobalISel: support swifterror attribute on AArch64.Tim Northover2019-05-241-2/+14
* [GlobalISel] Handle <1 x T> vector return types properly.Amara Emerson2019-05-061-11/+31
* [GlobalISel][AArch64] Allow CallLowering to handle types which are normallyAmara Emerson2019-04-091-7/+56
* [AArch64][GlobalISel] Fix i1 arguments not being zero-extended as required by...Amara Emerson2019-03-081-0/+3
* GlobalISel: Fix creating MMOs with align 0Matt Arsenault2019-01-311-2/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AArch64] Support adding X[8-15,18] registers as CSRs.Tri Vo2018-09-221-1/+8
* [AArch64] Support reserving x1-7 registers.Nick Desaulniers2018-09-071-1/+4
* [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per V...Alexander Ivchenko2018-08-021-17/+30
* [AArch64][GlobalISel] Fix fallbacks introduced in r336120 due to unselectable...Amara Emerson2018-07-031-2/+5
* [AArch64][GlobalISel] Any-extend vararg parameters to stack slot size on Darwin.Amara Emerson2018-07-021-0/+3
* [AArch64][GlobalISel] Zero-extend s1 values when returning.Amara Emerson2018-06-011-1/+6
* [GlobalISel][IRTranslator] Split aggregates during IR translation.Amara Emerson2018-05-161-0/+3
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
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