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* [SelectionDAG] Add support for vector demandedelts in MUL opcodesSimon Pilgrim2016-11-101-3/+5
| | | | llvm-svn: 286471
* [SelectionDAG] Add support for vector demandedelts in SRA opcodesSimon Pilgrim2016-11-101-1/+2
| | | | llvm-svn: 286461
* [DAGCombiner] Correctly extract the ConstOrConstSplat shift value for SHL nodesSimon Pilgrim2016-11-101-3/+2
| | | | | | | | We were failing to extract a constant splat shift value if the shifted value was being masked. The (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV) combine was unnecessarily preventing this. llvm-svn: 286454
* [SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodesSimon Pilgrim2016-11-101-2/+4
| | | | llvm-svn: 286448
* GlobalISel: fix typo. NFCTim Northover2016-11-091-2/+2
| | | | llvm-svn: 286408
* GlobalISel: translate invoke and landingpad instructionsTim Northover2016-11-091-1/+116
| | | | | | | Pretty bare-bones support for exception handling (no weird MSVC stuff, no SjLj etc), but it should get things going. llvm-svn: 286407
* [MachineScheduler] Comments fixing.Jonas Paulsson2016-11-091-1/+2
| | | | | | | | The name/comment of the third argument to the ScheduleDAGMI constructor is RemoveKillFlags and not IsPostRA. Only the comments are changed. Review: A Trick llvm-svn: 286350
* [CodeView] Hook up CodeViewRecordIO to type serialization path.Zachary Turner2016-11-082-97/+111
| | | | | | | | | | | | Previously support had been added for using CodeViewRecordIO to read (deserialize) CodeView type records. This patch adds support for writing those same records. With this patch, reading and writing of CodeView type records finally uses a single codepath. Differential Revision: https://reviews.llvm.org/D26253 llvm-svn: 286304
* Emit the DW_AT_type for a C++ static member definitionAdrian Prantl2016-11-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | if it is more specific than the one in its DW_AT_specification. If a static member is an array, the translation unit containing the member definition may have a more specific type (including its length) than TUs only seeing the class declaration. This patch adds a DW_AT_type to the member's DW_TAG_variable in addition to the DW_AT_specification in these cases. The member type in the DW_AT_specification still shows the more generic type (without the length) to avoid defeating type uniquing. The DWARF standard discourages “duplicating” a DW_AT_type in a member variable definition but doesn’t explicitly forbid it. Having the more specific type (with the array length) available is what allows the debugger to print the contents of a static array member variable. https://reviews.llvm.org/D26368 rdar://problem/28706946 llvm-svn: 286302
* GlobalISel: make sure debugging variables are appropriately elided in ↵David L. Jones2016-11-081-2/+4
| | | | | | | | | | | | | | | | release builds. Summary: There are two variables here that break. This change constrains both of them to debug builds (via DEBUG() or #ifndef NDEBUG). Reviewers: bkramer, t.p.northover Subscribers: mehdi_amini, vkalintiris Differential Revision: https://reviews.llvm.org/D26421 llvm-svn: 286300
* GlobalISel: allow CodeGen to fallback on VReg type/class issues.Tim Northover2016-11-082-25/+38
| | | | | | | | | After instruction selection we perform some checks on each VReg just before discarding the type information. These checks were assertions before, but that breaks the fallback path so this patch moves the logic into the main flow and reports a better error on failure. llvm-svn: 286289
* [GlobalISel] Dump all instructions inserted by selector.Ahmed Bougacha2016-11-081-3/+9
| | | | | | This is helpful when multiple instructions are inserted. llvm-svn: 286273
* [GlobalISel] Permit select() to erase.Ahmed Bougacha2016-11-081-5/+22
| | | | | | | | | | | Erasing reverse_iterators is problematic; iterate manually. While there, keep track of the range of inserted instructions. It can miss instructions inserted elsewhere, but those are harder to track. Differential Revision: http://reviews.llvm.org/D22924 llvm-svn: 286272
* [RegAllocGreedy] Another fix about NewVRegs for last chance recoloring after ↵Wei Mi2016-11-081-8/+5
| | | | | | | | | | | | | | | | | | r281783. About when we should move a vreg from CurrentNewVRegs to NewVRegs, if the vreg in CurrentNewVRegs was added into RecoloringCandidate and was evicted, it shouldn't be added to NewVRegs because its physical register will be restored at the end of tryLastChanceRecoloring after the recoloring failed. If the vreg in CurrentNewVRegs was not in RecoloringCandidate, i.e. it was evicted in selectOrSplitImpl inside tryRecoloringCandidates, its physical register will not be restored even if the recoloring failed. In that case, we need to add the vreg to NewVRegs. Same as r281783, the problem was seen on out-of-tree target and we didn't have a test case that reproduce the problem with in-tree targets. llvm-svn: 286259
* [TargetLowering] Fix undef vector element issue with true/false result handlingSimon Pilgrim2016-11-081-10/+10
| | | | | | | | | | | | | | Fixed an issue with vector usage of TargetLowering::isConstTrueVal / TargetLowering::isConstFalseVal boolean result matching. The comment said we shouldn't handle constant splat vectors with undef elements. But the the actual code was returning false if the build vector contained no undef elements.... This patch now ignores the number of undefs (getConstantSplatNode will return null if the build vector is all undefs). The change has also unearthed a couple of missed opportunities in AVX512 comparison code that will need to be addressed. Differential Revision: https://reviews.llvm.org/D26031 llvm-svn: 286238
* [VectorLegalizer] Expansion of CTLZ using CTPOP when possibleSimon Pilgrim2016-11-081-6/+50
| | | | | | | | | | This patch avoids scalarization of CTLZ by instead expanding to use CTPOP (ref: "Hacker's Delight") when the necessary operations are available. This also adds the necessary cost models for X86 SSE2 targets (the main beneficiary) to ensure vectorization only happens when its useful. Differential Revision: https://reviews.llvm.org/D25910 llvm-svn: 286233
* GlobalISel: improve error diagnostics when IRTranslation fails.Tim Northover2016-11-081-3/+9
| | | | llvm-svn: 286190
* Add -O0 support for @llvm.invariant.group.barrier by discarding it if it ↵Richard Smith2016-11-072-0/+2
| | | | | | | | gets to ISel. Differential Revision: https://reviews.llvm.org/D26292 llvm-svn: 286119
* [SelectionDAG] Add support for vector demandedelts in XOR opcodesSimon Pilgrim2016-11-061-2/+4
| | | | llvm-svn: 286075
* [SelectionDAG] Add support for vector demandedelts in OR opcodesSimon Pilgrim2016-11-061-2/+4
| | | | llvm-svn: 286071
* Comment rewording in MachineScheduler.cpp.Jonas Paulsson2016-11-041-3/+2
| | | | | Author: A Trick llvm-svn: 285991
* Hoist check for TLI above all of the attempts to use it (including oneChandler Carruth2016-11-041-2/+6
| | | | | | | | | | | | | | | | | | | | | | of which that is hidden inside a separate function call) and helpfully before building expensive transaction infrastructure. This will avoid crashing when running CGP in a generic mode if we ever managed to hit this case. Note that I spent some time looking at alternatives. CGP is actually used without a TM or TLI in order to do some target-independent testing. Further, all of the neighboring optimization techniques actually have some paths that are effective even in the absence of TLI so this seemed the correct scope at which to check and bypass logic. It still isn't clear that long-term support for missing TM/TLI is the right cost/benefit tradeoff for CGP -- we seem to get relatively little for it and the code is just littered with checks (and assumptions which I suspect are still missing some checks). This at least fixes the potential bug in this code spotted by PVS-Studio, so we've got that going for us. ;] llvm-svn: 285987
* Add DWARF debug info support for C++11 inline namespaces.Adrian Prantl2016-11-031-0/+2
| | | | | | | | | This implements the DWARF 5 DW_AT_export_symbols feature: http://dwarfstd.org/ShowIssue.php?issue=141212.1 <rdar://problem/18616046> llvm-svn: 285959
* DAGCombiner: fix use-after-free when merging consecutive storesNicolai Haehnle2016-11-031-18/+22
| | | | | | | | | | | | | | | Summary: Have MergeConsecutiveStores explicitly return information about the stores that were merged, so that we can safely determine whether the starting node has been freed. Reviewers: chandlerc, bogner, niravd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D25601 llvm-svn: 285916
* Expandload and Compressstore intrinsicsElena Demikhovsky2016-11-034-22/+72
| | | | | | | | 2 new intrinsics covering AVX-512 compress/expand functionality. This implementation includes syntax, DAG builder, operation lowering and tests. Does not include: handling of illegal data types, codegen prepare pass and the cost model. llvm-svn: 285876
* Emit S_COMPILE3 record once per TU rather than once per functionAdrian McCarthy2016-11-021-2/+5
| | | | | | This has some ripple effects in several tests. llvm-svn: 285862
* Add CodeViewRecordIO for reading and writing.Zachary Turner2016-11-021-16/+14
| | | | | | | | | | | | | | | Using a pattern similar to that of YamlIO, this allows us to have a single codepath for translating codeview records to and from serialized byte streams. The current patch only hooks this up to the reading of CodeView type records. A subsequent patch will hook it up for writing of CodeView type records, and then a third patch will hook up the reading and writing of CodeView symbols. Differential Revision: https://reviews.llvm.org/D26040 llvm-svn: 285836
* Fix Clang-tidy readability-redundant-string-cstr warningsMalcolm Parsons2016-11-021-1/+1
| | | | | | | | | | Reviewers: beanz, lattner, jlebar Subscribers: jholewinski, llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D26235 llvm-svn: 285832
* Improve and cleanup comments in DwarfExpression.hAdrian Prantl2016-11-021-15/+14
| | | | llvm-svn: 285829
* BranchRelaxation: Fix computing indirect branch block sizeMatt Arsenault2016-11-021-17/+17
| | | | llvm-svn: 285828
* Simplify control flow in the the DWARF expression compilerAdrian Prantl2016-11-024-69/+105
| | | | | | by refactoring common code into a DwarfExpressionCursor wrapper. llvm-svn: 285827
* Emit DW_OP_piece also if the previous value was a constant.Adrian Prantl2016-11-021-4/+6
| | | | | | This fixes a bug in the DWARF backend. llvm-svn: 285826
* Use !operator to test if APInt is zero/non-zero. NFCI.Simon Pilgrim2016-11-021-3/+3
| | | | | | Avoids APInt construction and slower comparisons. llvm-svn: 285822
* Simplify.Joerg Sonnenberger2016-11-021-2/+2
| | | | llvm-svn: 285802
* Move the initialization of PreferredLoopExit into runOnMachineFunction to be ↵Eric Christopher2016-11-011-1/+5
| | | | | | near the other function specific initializations. llvm-svn: 285758
* Fix uninitialized access in MachineBlockPlacement.Sam McCall2016-11-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: Currently PreferredLoopExit is set only in buildLoopChains, which is never called if there are no MachineLoops. MSan is currently broken by this: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/145/steps/check-llvm%20msan/logs/stdio This is a naive fix to get things green again. iteratee: you may have a better fix. This change will also mean PreferredLoopExit will not carry over if buildCFGChains() is called a second time in runOnMachineFunction, this appears to be the right thing. Reviewers: bkramer, iteratee, echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D26069 llvm-svn: 285757
* BranchRelaxation: Expand unconditional branches firstMatt Arsenault2016-11-011-15/+22
| | | | | | | | | | | | | It's likely if a conditional branch needs to be expanded, the following unconditional branch will also need expansion. By expanding the unconditional branch first, the conditional branch can be simply inverted to jump over the inserted indirect branch block. If the conditional branch is expanded first, it results in an additional branch. This avoids test regressions in future commits. llvm-svn: 285722
* [DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded ↵Sanjay Patel2016-10-311-7/+18
| | | | | | | | | | | | | | | | bits (PR30841) This bug was exposed by using nsw/nuw for more aggressive folds in: https://reviews.llvm.org/rL284844 The changes mimic the IR demanded bits logic in InstCombiner::SimplifyDemandedUseBits(), but we can't just flip flag bits in the DAG; we have to create a new node that has the bits cleared. This should fix: https://llvm.org/bugs/show_bug.cgi?id=30841 llvm-svn: 285656
* DebugInfo: make DW_TAG_atomic_type validVictor Leschuk2016-10-313-3/+8
| | | | | | | | | | | | | | DW_TAG_atomic_type was already included in Dwarf.defs and emitted correctly, however Verifier didn't recognize it as valid. Thus we introduce the following changes: * Make DW_TAG_atomic_type valid tag for IR and DWARF (enabled only with -gdwarf-5) * Add it to related docs * Add DebugInfo tests Differential Revision: https://reviews.llvm.org/D26144 llvm-svn: 285624
* GlobalISel: translate stack protector intrinsicsTim Northover2016-10-312-13/+63
| | | | llvm-svn: 285614
* [DAG] x | x --> xSanjay Patel2016-10-301-0/+4
| | | | llvm-svn: 285522
* [DAG] x & x --> xSanjay Patel2016-10-301-0/+4
| | | | llvm-svn: 285521
* [DAGCombiner] (REAPPLIED) Add vector demanded elements support to ↵Simon Pilgrim2016-10-291-13/+111
| | | | | | | | | | | | | | | | | | | | computeKnownBits Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements. This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1. The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used. I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course. DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit. This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander! Differential Revision: https://reviews.llvm.org/D25691 llvm-svn: 285494
* [DAGCombiner] Fix a crash visiting `AND` nodes.Davide Italiano2016-10-281-1/+6
| | | | | | | | | | Instead of asserting that the shift count is != 0 we just bail out as it's not profitable trying to optimize a node which will be removed anyway. Differential Revision: https://reviews.llvm.org/D26098 llvm-svn: 285480
* SDAG: Make sure we use an allocatable reg class when we create this vregJustin Bogner2016-10-281-0/+2
| | | | | | | As per the discussion on r280783, if constrainRegClass fails we need to call getAllocatableClass like we did before that commit. llvm-svn: 285467
* Handle non-~0 lane masks on live-in registers in LivePhysRegsKrzysztof Parzyszek2016-10-281-2/+3
| | | | | | | | | | | | | | | | | When LivePhysRegs adds live-in registers, it recognizes ~0 as a special lane mask indicating the entire register. If the lane mask is not ~0, it will only add the subregisters that overlap the specified lane mask. The problem is that if a live-in register does not have subregisters, and the lane mask is not ~0, it will not be added to the live set. (The given lane mask may simply be the lane mask of its register class.) If a register does not have subregisters, add it to the live set if the lane mask is non-zero. Differential Revision: https://reviews.llvm.org/D26094 llvm-svn: 285440
* MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun2016-10-286-7/+6
| | | | llvm-svn: 285423
* TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down.Matthias Braun2016-10-281-3/+3
| | | | | | | | | TargetPassConfig::addMachinePasses() does some housekeeping first: Handling the -print-machineinstrs flag and doing an initial printing "After Instruction Selection". There is no reason for RegUsageInfoProp to run before those two steps. llvm-svn: 285422
* Import/update constants from the DWARF 5 public review draft document.Adrian Prantl2016-10-281-2/+2
| | | | | | https://reviews.llvm.org/D26051 llvm-svn: 285421
* [SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has ↵Simon Pilgrim2016-10-281-0/+4
| | | | | | | | no known bits No need to check the remaining elements - no common known bits are available. llvm-svn: 285399
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