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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 13:52:42 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-10 13:52:42 +0000 |
| commit | 3bf99c056a99348943b3086438baf5742ef00a97 (patch) | |
| tree | 851a4a055704263d9a6cdcdaaf7f6208f0706b3c /llvm/lib/CodeGen | |
| parent | ede8ad7c5abf944f26eb60d3253bdd419bdc22ba (diff) | |
| download | bcm5719-llvm-3bf99c056a99348943b3086438baf5742ef00a97.tar.gz bcm5719-llvm-3bf99c056a99348943b3086438baf5742ef00a97.zip | |
[SelectionDAG] Add support for vector demandedelts in SHL/SRL opcodes
llvm-svn: 286448
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 09f3a006cb8..6d25ead3fe3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2244,7 +2244,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, break; case ISD::SHL: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { - computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1); + computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts, + Depth + 1); KnownZero = KnownZero << *ShAmt; KnownOne = KnownOne << *ShAmt; // Low bits are known zero. @@ -2253,7 +2254,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, break; case ISD::SRL: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { - computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1); + computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts, + Depth + 1); KnownZero = KnownZero.lshr(*ShAmt); KnownOne = KnownOne.lshr(*ShAmt); // High bits are known zero. |
