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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-06 16:49:19 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2016-11-06 16:49:19 +0000 |
| commit | 39df78e384243f63f2da07f2d160579d913b380c (patch) | |
| tree | d16235c1d863617c5b73e19516540adef6d71390 /llvm/lib/CodeGen | |
| parent | 3ac353cb51570049e0c9e0b174fb8dc78ed30473 (diff) | |
| download | bcm5719-llvm-39df78e384243f63f2da07f2d160579d913b380c.tar.gz bcm5719-llvm-39df78e384243f63f2da07f2d160579d913b380c.zip | |
[SelectionDAG] Add support for vector demandedelts in XOR opcodes
llvm-svn: 286075
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 430f39d9b52..09f3a006cb8 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2153,8 +2153,10 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero, KnownOne |= KnownOne2; break; case ISD::XOR: { - computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); - computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); + computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, DemandedElts, + Depth + 1); + computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, DemandedElts, + Depth + 1); // Output known-0 bits are known if clear or set in both the LHS & RHS. APInt KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); |
