| Commit message (Collapse) | Author | Age | Files | Lines |
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everyone is doing this these days :-). Patch by Daniel M Gessel!
llvm-svn: 60958
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do an extending load of the 4 bytes rather than a
potentially illegal (type) i32 load followed by a
sign extend.
llvm-svn: 60945
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Added support for TRUNC v8i16 to v8i8 for X86 (MMX)
llvm-svn: 60916
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ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.
Similar for SUB and MUL instructions.
llvm-svn: 60915
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llvm-svn: 60869
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llvm-svn: 60867
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llvm-svn: 60866
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vec_extract-sse4.ll.
llvm-svn: 60865
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llvm-svn: 60861
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them. The DAG combiner expects that nodes that are transformed have one value
result.
llvm-svn: 60857
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for promoted integer types, eg: i16 on ppc-32, or
i24 on any platform. Complete support for arbitrary
precision integers would require handling expanded
integer types, eg: i128, but I couldn't be bothered.
llvm-svn: 60834
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bit convert that changes the number of elements of a shuffle.
llvm-svn: 60829
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some overflow issues. Patch by Thomas Jablin.
llvm-svn: 60828
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llvm-svn: 60826
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llvm-svn: 60818
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node latencies. Use CalcLatency instead of manual code in
CalculatePriorities to keep it consistent. Previously it
computed slightly different results.
llvm-svn: 60817
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- Emit DW_AT_byte_size for struct and union of size zero.
- Emit DW_AT_declaration for forward type declaration.
llvm-svn: 60812
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The Cost field is removed. It was only being used in a very limited way,
to indicate when the scheduler should attempt to protect a live register,
and it isn't really needed to do that. If we ever want the scheduler to
start inserting copies in non-prohibitive situations, we'll have to
rethink some things anyway.
A Latency field is added. Instead of giving each node a single
fixed latency, each edge can have its own latency. This will eventually
be used to model various micro-architecture properties more accurately.
The PointerIntPair class and an internal union are now used, which
reduce the overall size.
llvm-svn: 60806
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llvm-svn: 60804
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target-independent way of determining overflow on multiplication. It's very
tricky. Patch by Zoltan Varga!
llvm-svn: 60800
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essential problem was that the DAG can contain
random unused nodes which were never analyzed.
When remapping a value of a node being processed,
such a node may become used and need to be analyzed;
however due to operands being transformed during
analysis the node may morph into a different one.
Users of the morphing node need to be updated, and
this wasn't happening. While there I added a bunch
of documentation and sanity checks, so I (or some
other poor soul) won't have to scratch their head
over this stuff so long trying to remember how it
was all supposed to work next time some obscure
problem pops up! The extra sanity checking exposed
a few places where invariants weren't being preserved,
so those are fixed too. Since some of the sanity
checking is expensive, I added a flag to turn it
on. It is also turned on when building with
ENABLE_EXPENSIVE_CHECKS=1.
llvm-svn: 60797
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llvm-svn: 60771
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llvm-svn: 60769
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one of its operand.
llvm-svn: 60749
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Fix the shift amount when unrolling a vector shift into scalar shifts.
Fix problem in getShuffleScalarElt where it assumes that the input of
a bit convert must be a vector.
llvm-svn: 60740
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pipeline model.
llvm-svn: 60733
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llvm-svn: 60707
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and use it in x86 address mode folding. Also, make
getRegForValue return 0 for illegal types even if it has a
ValueMap for them, because Argument values are put in the
ValueMap. This fixes PR3181.
llvm-svn: 60696
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llvm-svn: 60684
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llvm-svn: 60683
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live interval updating.
llvm-svn: 60652
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constpool into a use, the rewrite happens at time of spill (not in VirtRegMap). Later on, if the GlobalBaseReg is spilled, the spiller can see the use uses GlobalBaseReg and do the right thing.
llvm-svn: 60596
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llvm-svn: 60592
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llvm-svn: 60586
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changing the stack slots on an instruction, to keep them
consistent with the actual memory addresses.
llvm-svn: 60584
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While they appear to provide a normal clobbering def, they don't
in the case of the awkward IMPLICIT_DEF+INSERT_SUBREG idiom. It
would be good to change INSERT_SUBREG; until then, this change
allows post-regalloc scheduling to cope in a mildly conservative
way.
llvm-svn: 60583
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llvm-svn: 60553
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number of bytes for types such as i1 which are not
a multiple of 8 bits in length.
llvm-svn: 60543
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llvm-svn: 60525
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llvm-svn: 60524
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the main thing this covers is spills to distinct spill slots.
llvm-svn: 60517
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issues with subreg operands and tied operands.
llvm-svn: 60510
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on PseudoSourceValue values. This also fixes a FIXME in
lib/VMCode/AsmWriter.cpp.
llvm-svn: 60507
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llvm-svn: 60500
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an area where eventually it would be good to use target-dependent
information.
llvm-svn: 60498
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examining non-anti-dependence edges.
llvm-svn: 60496
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llvm-svn: 60495
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parts, and add target-independent code to add/preserve
MachineMemOperands.
llvm-svn: 60488
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llvm-svn: 60487
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a new node if the node was actually remapped.
llvm-svn: 60482
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