Redo the arithmetic with overflow architecture. I was changing the semantics of

ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace
the intrinsic with an ISD::SADDO node. Then custom lower that into an
X86ISD::ADD node with a associated SETCC that checks the correct condition code
(overflow or carry). Then that gets lowered into the correct X86::ADDOvf
instruction.

Similar for SUB and MUL instructions.

llvm-svn: 60915

1 files changed, 0 insertions, 15 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 314697df177..65384176558 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -967,11 +967,6 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
     if (FoldedVOp.getNode()) return FoldedVOp;
   }
 
-  if (N->getNumValues() != 1)
-    // FIXME: DAG combiner cannot handle arithmetic operators which produce
-    // multiple results.
-    return SDValue();
-  
   // fold (add x, undef) -> undef
   if (N0.getOpcode() == ISD::UNDEF)
     return N0;
@@ -1167,11 +1162,6 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
     if (FoldedVOp.getNode()) return FoldedVOp;
   }
 
-  if (N->getNumValues() != 1)
-    // FIXME: DAG combiner cannot handle arithmetic operators which produce
-    // multiple results.
-    return SDValue();
-  
   // fold (sub x, x) -> 0
   if (N0 == N1)
     return DAG.getConstant(0, N->getValueType(0));
@@ -1230,11 +1220,6 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
     if (FoldedVOp.getNode()) return FoldedVOp;
   }
   
-  if (N->getNumValues() != 1)
-    // FIXME: DAG combiner cannot handle arithmetic operators which produce
-    // multiple results.
-    return SDValue();
-    
   // fold (mul x, undef) -> 0
   if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
     return DAG.getConstant(0, VT);