| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [DAGCombine] Ensure SDNode use iterator is incremented properly. | Amara Emerson | 2018-01-04 | 1 | -2/+2 |
| * | [DAGCombine] Handle out of range EXTRACT_VECTOR_ELT indices | Simon Pilgrim | 2018-01-03 | 2 | -1/+5 |
| * | Revert r321089: "[DAG] Elide overlapping store" (and subsequent fix in r321204) | Daniel Jasper | 2018-01-02 | 1 | -21/+21 |
| * | [DAGCombine] Fix for PR35765 | Sam Parker | 2018-01-02 | 1 | -1/+0 |
| * | [SelectionDAG] Teach WidenVecOp_Convert to widen the operation if a widened r... | Craig Topper | 2018-01-02 | 1 | -4/+13 |
| * | [SelectionDAG] Remove ifs on getTypeAction being TypeWidenVector from some of... | Craig Topper | 2018-01-02 | 1 | -9/+11 |
| * | [SelectionDAG][X86][AArch64] Require targets to specify the promotion type wh... | Craig Topper | 2018-01-01 | 1 | -37/+21 |
| * | Use phi ranges to simplify code. No functionality change intended. | Benjamin Kramer | 2017-12-30 | 4 | -26/+22 |
| * | Avoid modifying DbgInfo while looping in salvageDebuginfo | Dimitry Andric | 2017-12-28 | 1 | -1/+6 |
| * | [SelectionDAG] Add creating new node debug messages for load, store, gather, ... | Craig Topper | 2017-12-28 | 1 | -8/+24 |
| * | [SelectionDAG] Add some debug print messages to LegalizeVectorOps. | Craig Topper | 2017-12-28 | 1 | -2/+15 |
| * | [DAGCombine] foldBinOpIntoSelect can fail to constant fold in some cases. | Simon Pilgrim | 2017-12-27 | 1 | -6/+8 |
| * | [DAGCombine] visitANDLike - ensure APInt is is in range for getSExtValue/getZ... | Simon Pilgrim | 2017-12-26 | 1 | -4/+7 |
| * | [DAGCombine] Don't combine (and (setne X, 0), (setne X, -1)) --> (setuge (add... | Simon Pilgrim | 2017-12-26 | 1 | -1/+2 |
| * | [DAGCombiners] Don't turn ANDs to shuffles with zero so early. Give some othe... | Craig Topper | 2017-12-24 | 1 | -7/+8 |
| * | [SelectionDAG] Teach SelectionDAG::getNode to constant fold zext/aext/sext of... | Craig Topper | 2017-12-23 | 1 | -0/+3 |
| * | [SelectionDAG][X86] Don't use ->getValueType(0) after a call to getOperand to... | Craig Topper | 2017-12-23 | 3 | -7/+7 |
| * | [DAG] Add missing case check from findbaseoffset merge from r321389. | Nirav Dave | 2017-12-22 | 1 | -2/+4 |
| * | Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI. | Nirav Dave | 2017-12-22 | 2 | -70/+27 |
| * | Revert "[DAG] Integrate findBaseOffset address analyses to BaseIndexOffset. N... | Nirav Dave | 2017-12-22 | 2 | -27/+70 |
| * | [SelectionDAG] Reverse the order of operands in the ISD::ADD created by Targe... | Craig Topper | 2017-12-22 | 1 | -1/+1 |
| * | [DAG] Integrate findBaseOffset address analyses to BaseIndexOffset. NFCI. | Nirav Dave | 2017-12-22 | 2 | -70/+27 |
| * | [DAGCombine] Revert r321259 | Sam Parker | 2017-12-22 | 1 | -26/+0 |
| * | [DAGCombiner] Remove (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) fold. NFCI. | Simon Pilgrim | 2017-12-21 | 1 | -15/+0 |
| * | [DAGCombiner] Generalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) comb... | Simon Pilgrim | 2017-12-21 | 1 | -10/+10 |
| * | [DAGCombiner] Generalize (and (or x, C), D) -> D iff (C & D) == D combine to ... | Simon Pilgrim | 2017-12-21 | 1 | -4/+6 |
| * | [DAGCombine] Improve ReduceLoadWidth for SRL | Sam Parker | 2017-12-21 | 1 | -0/+26 |
| * | DAG: Tolerate non-MemSDNodes for OPC_RecordMemRef | Matt Arsenault | 2017-12-20 | 1 | -8/+24 |
| * | [DAG] Fix condition on overlapping store check. | Nirav Dave | 2017-12-20 | 1 | -2/+2 |
| * | Add optional SelectionDAG* parameter to SValue::dump and SDValue::dumpr | Krzysztof Parzyszek | 2017-12-20 | 1 | -4/+4 |
| * | Silence a bunch of implicit fallthrough warnings | Adrian Prantl | 2017-12-19 | 2 | -1/+2 |
| * | [DAG] Elide overlapping store | Nirav Dave | 2017-12-19 | 1 | -21/+21 |
| * | [DAGCombine] Move AND nodes to multiple load leaves | Sam Parker | 2017-12-18 | 1 | -0/+144 |
| * | Fix unused variable in non-assert builds | Matthias Braun | 2017-12-15 | 1 | -2/+1 |
| * | MachineFunction: Return reference from getFunction(); NFC | Matthias Braun | 2017-12-15 | 6 | -31/+29 |
| * | [SelectionDAG][X86] Fix insert_vector_elt lowering for v32i1/v64i1 with non-c... | Craig Topper | 2017-12-15 | 1 | -4/+25 |
| * | [SelectionDAG] Make getNode calls that take an ArrayRef of SDValue for operan... | Craig Topper | 2017-12-15 | 1 | -4/+7 |
| * | EmitFuncArgumentDbgValue: Prefer stack slots over registers for stack arguments | Adrian Prantl | 2017-12-14 | 1 | -7/+7 |
| * | TLI: Allow using PSV for intrinsic mem operands | Matt Arsenault | 2017-12-14 | 1 | -1/+3 |
| * | Fix many -Wsign-compare and -Wtautological-constant-compare warnings. | Zachary Turner | 2017-12-14 | 1 | -1/+1 |
| * | DAG: Expose all MMO flags in getTgtMemIntrinsic | Matt Arsenault | 2017-12-14 | 2 | -18/+10 |
| * | Revert "[DAGCombine] Move AND nodes to multiple load leaves" | Benjamin Kramer | 2017-12-14 | 1 | -124/+0 |
| * | [DAGCombine] Move AND nodes to multiple load leaves | Sam Parker | 2017-12-14 | 1 | -0/+124 |
| * | [SelectionDAG][X86] Improve legalization of v32i1 CONCAT_VECTORS of v16i1 for... | Craig Topper | 2017-12-14 | 1 | -0/+15 |
| * | [SelectionDAG] When legalizing the result type of CONCAT_VECTORS, take into a... | Craig Topper | 2017-12-14 | 1 | -3/+8 |
| * | Remove redundant includes from lib/CodeGen. | Michael Zolotukhin | 2017-12-13 | 3 | -6/+0 |
| * | [DAG] Promote ADDCARRY / SUBCARRY | Roger Ferrer Ibanez | 2017-12-13 | 1 | -1/+24 |
| * | [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579) | Sanjay Patel | 2017-12-11 | 1 | -1/+2 |
| * | [DAGCombiner] Add combined indexed load to the work list | Nemanja Ivanovic | 2017-12-11 | 1 | -0/+1 |
| * | [ARM] Use ADDCARRY / SUBCARRY | Roger Ferrer Ibanez | 2017-12-11 | 1 | -1/+2 |
