summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Commit message (Expand)AuthorAgeFilesLines
* [TargetLowering] Fix another potential FPE in expandFP_TO_UINTCraig Topper2019-12-061-15/+15
* [SelectionDAG] Expand nnan FMINNUM/FMAXNUM to select sequenceUlrich Weigand2019-12-041-0/+20
* [TargetLowering] Merge ExpandChainLibCall with makeLibCallCraig Topper2019-11-251-36/+6
* [Codegen] TargetLowering::prepareUREMEqFold(): `x u% C1 ==/!= C2` (PR35479)Roman Lebedev2019-11-221-9/+28
* [Codegen] TargetLowering::prepareUREMEqFold(): `x u% C1 ==/!= C2` with tautol...Roman Lebedev2019-11-221-25/+73
* [SelectionDAG] Merge the two identical ExpandChainLibCall methods from Legali...Craig Topper2019-11-181-0/+34
* [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4)joanlluch2019-11-131-4/+4
* [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (3)joanlluch2019-11-111-6/+9
* [SDAG] reduce code duplication; NFCSanjay Patel2019-11-071-18/+11
* [SDAG] reduce code duplication; NFCSanjay Patel2019-11-071-4/+4
* [TargetLowering] Move the setBooleanContents check on (xor (setcc), (setcc)) ...Craig Topper2019-11-011-8/+13
* [TargetLowering] Add getBooleanContents contents check to "SETCC (SETCC), [0|...Craig Topper2019-10-271-2/+5
* Revert 4334892e7b "[DAGCombine][ARM] x ==/!= c -> (x - c) ==/!= 0 iff '-c'...Hans Wennborg2019-10-231-65/+0
* [TargetLowering] optimizeSetCCToComparisonWithZero(): add extra sanity checks...Roman Lebedev2019-10-231-2/+6
* [DAGCombine][ARM] x ==/!= c -> (x - c) ==/!= 0 iff '-c' can be folded into...Roman Lebedev2019-10-221-0/+61
* [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold ...Sanjay Patel2019-10-191-12/+14
* [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (...Simon Pilgrim2019-10-011-0/+240
* [globalisel][knownbits] Allow targets to call GISelKnownBits::computeKnownBit...Daniel Sanders2019-09-301-2/+3
* [TargetLowering] Simplify expansion of S{ADD,SUB}ORoger Ferrer Ibanez2019-09-301-18/+13
* Revert r372333: [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to...Ilya Biryukov2019-09-241-240/+0
* [SelectionDAG][Mips][Sparc] Don't allow SimplifyDemandedBits to constant fold...Craig Topper2019-09-201-0/+2
* [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (...Simon Pilgrim2019-09-191-0/+240
* [DAG] Add SelectionDAG::MaxRecursionDepth constantSimon Pilgrim2019-09-191-3/+4
* [SimplifyDemandedBits] Use APInt::intersects to instead of ANDing and compari...Craig Topper2019-09-171-2/+3
* [TargetLowering] SimplifyDemandedBits - add EXTRACT_SUBVECTOR support.Simon Pilgrim2019-09-141-0/+15
* [SDAG] Update generic code to conservatively check for isAtomic in addition t...Philip Reames2019-09-121-1/+1
* GlobalISel: add combiner to form indexed loads.Tim Northover2019-09-091-1/+1
* [CodeGen] Handle SMULFIXSAT with scale zero in TargetLowering::expandFixedPoi...Bjorn Pettersson2019-09-071-10/+21
* [Intrinsic] Add the llvm.umul.fix.sat intrinsicBjorn Pettersson2019-09-071-19/+56
* [TargetLowering] Fix Bugzilla ID 43183 to avoid soften comparison broken with...Shiva Chen2019-09-011-10/+7
* [TargetLowering] SimplifyDemandedBits ADD/SUB/MUL - correctly inherit SDNodeF...Simon Pilgrim2019-08-301-4/+2
* [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCallShiva Chen2019-08-281-5/+25
* [FPEnv] Add fptosi and fptoui constrained intrinsics.Kevin P. Neal2019-08-281-9/+39
* [TargetLowering] Add buildLegalVectorShuffle facility to help build legal shu...Amaury Sechet2019-08-281-5/+24
* [SelectionDAG][X86] Enable iX SimplifyDemandedBits to vXi1 SimplifyDemandedVe...Craig Topper2019-08-231-3/+1
* [TargetLowering] Remove optional arguments passing to makeLibCallShiva Chen2019-08-221-20/+18
* [TargetLowering] x s% C == 0 fold: vector divisor with INT_MIN handlingRoman Lebedev2019-08-191-13/+66
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-1/+1
* Remove BitVector.h include. NFCI.Simon Pilgrim2019-08-151-1/+0
* [CodeGen][SelectionDAG] More efficient code for X % C == 0 (SREM case)Roman Lebedev2019-08-131-5/+221
* [TargetLowering][NFC] prepareUREMEqFold(): fixup commentRoman Lebedev2019-08-131-1/+1
* Revert r368276 "[TargetLowering] SimplifyDemandedBits - call SimplifyMultiple...Hans Wennborg2019-08-131-11/+0
* [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim2019-08-121-0/+5
* [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim2019-08-081-0/+11
* [TargetLowering] SimplifyDemandedBits - call SimplifyMultipleUseDemandedBits ...Simon Pilgrim2019-08-071-4/+19
* [GISel]: Add GISelKnownBits analysisAditya Nandakumar2019-08-061-0/+6
* [TargetLowering] SimplifyMultipleUseDemandedBits - return UNDEF for undemande...Simon Pilgrim2019-08-061-1/+10
* [TargetLowering][X86] Teach SimplifyDemandedVectorElts to replace the base ve...Craig Topper2019-08-041-0/+9
* Emit diagnostic if an inline asm constraint requires an immediateBill Wendling2019-08-031-7/+11
* [TargetLowering] SimplifyMultipleUseDemandedBits - don't assume INSERT_VECTOR...Simon Pilgrim2019-08-021-1/+1
OpenPOWER on IntegriCloud