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author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-09-14 16:38:26 +0000 |
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committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-09-14 16:38:26 +0000 |
commit | b743e94cdca985cb676049290af4f49b6e49572f (patch) | |
tree | 6581bff4728dbc834a234ecf2f3fc520c3acde24 /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
parent | 9060643380b3c66233dbce64489fce1916a48d98 (diff) | |
download | bcm5719-llvm-b743e94cdca985cb676049290af4f49b6e49572f.tar.gz bcm5719-llvm-b743e94cdca985cb676049290af4f49b6e49572f.zip |
[TargetLowering] SimplifyDemandedBits - add EXTRACT_SUBVECTOR support.
Call SimplifyDemandedBits on the source vector.
llvm-svn: 371923
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 4fc9f2465d3..41b3ba1733d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -907,6 +907,21 @@ bool TargetLowering::SimplifyDemandedBits( } break; } + case ISD::EXTRACT_SUBVECTOR: { + // If index isn't constant, assume we need all the source vector elements. + SDValue Src = Op.getOperand(0); + ConstantSDNode *SubIdx = dyn_cast<ConstantSDNode>(Op.getOperand(1)); + unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); + APInt SrcElts = APInt::getAllOnesValue(NumSrcElts); + if (SubIdx && SubIdx->getAPIntValue().ule(NumSrcElts - NumElts)) { + // Offset the demanded elts by the subvector index. + uint64_t Idx = SubIdx->getZExtValue(); + SrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); + } + if (SimplifyDemandedBits(Src, DemandedBits, SrcElts, Known, TLO, Depth + 1)) + return true; + break; + } case ISD::CONCAT_VECTORS: { Known.Zero.setAllBits(); Known.One.setAllBits(); |