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author | Craig Topper <craig.topper@intel.com> | 2019-09-20 16:49:51 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2019-09-20 16:49:51 +0000 |
commit | 1b7b4b467f03322f37b20ccee5cdef0c9ecec5d4 (patch) | |
tree | 6b287e8419167bbb4ca5f698c6e139f6b5c266e7 /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
parent | f6398fb72c9e2d224ecc837d0e5713e008afbcb2 (diff) | |
download | bcm5719-llvm-1b7b4b467f03322f37b20ccee5cdef0c9ecec5d4.tar.gz bcm5719-llvm-1b7b4b467f03322f37b20ccee5cdef0c9ecec5d4.zip |
[SelectionDAG][Mips][Sparc] Don't allow SimplifyDemandedBits to constant fold TargetConstant nodes to a Constant.
Summary:
After the switch in SimplifyDemandedBits, it tries to create a
constant when possible. If the original node is a TargetConstant
the default in the switch will call computeKnownBits on the
TargetConstant which will succeed. This results in the
TargetConstant becoming a Constant. But TargetConstant exists to
avoid being changed.
I've fixed the two cases that relied on this in tree by explicitly
making the nodes constant instead of target constant. The Sparc
case is an old bug. The Mips case was recently introduced now that
ImmArg on intrinsics gets turned into a TargetConstant when the
SelectionDAG is created. I've removed the ImmArg since it lowers
to generic code.
Reviewers: arsenm, RKSimon, spatel
Subscribers: jyknight, sdardis, wdng, arichardson, hiraditya, fedor.sergeev, jrtc27, atanasyan, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67802
llvm-svn: 372409
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 0b6f8ba4257..0ab2f5a292a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -805,6 +805,8 @@ bool TargetLowering::SimplifyDemandedBits( KnownBits Known2, KnownOut; switch (Op.getOpcode()) { + case ISD::TargetConstant: + llvm_unreachable("Can't simplify this node"); case ISD::SCALAR_TO_VECTOR: { if (!DemandedElts[0]) return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); |