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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
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* Prune Analysis includes from SelectionDAG.hReid Kleckner2019-10-191-1/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* ScheduleDAG: Cleanup dumping code; NFCMatthias Braun2018-09-191-2/+2
* [CodeGen] Fix inconsistent declaration parameter nameFangrui Song2018-07-161-1/+1
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
* [Target] Fix some Clang-tidy modernize and Include What You Use warnings; oth...Eugene Zelenko2017-01-111-3/+16
* [SelectionDAG] Remove dead code. NFC.Benjamin Kramer2015-10-151-6/+0
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
* Avoid a Symbol -> Name -> Symbol conversion.Rafael Espindola2015-06-221-0/+1
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-1/+1
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check i...Craig Topper2014-04-161-1/+1
* [C++11] Add 'override' keyword to virtual methods that override their base cl...Craig Topper2014-03-081-3/+3
* Revert "Give internal classes hidden visibility."Benjamin Kramer2013-09-111-1/+1
* Give internal classes hidden visibility.Benjamin Kramer2013-09-111-1/+1
* Fix #includes, so we include only what we really need.Jakub Staszak2013-02-201-1/+1
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-131-2/+2
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-2/+2
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-111-2/+2
* Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng2012-10-171-1/+2
* misched: remove forceUnitLatencies. Defaults are handled by the default Sched...Andrew Trick2012-10-081-0/+6
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-071-0/+1
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-6/+0
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-6/+6
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-4/+5
* misched preparation: modularize schedule emission.Andrew Trick2012-03-071-0/+8
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+2
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-0/+4
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-071-0/+2
* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ...Andrew Trick2012-03-071-1/+1
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-181-0/+1
* The index stored in the RegDefIter is one after the current index. When gett...Owen Anderson2011-06-271-1/+1
* Add a new MVT::untyped. This will be used in future work for modelling ISA f...Owen Anderson2011-06-151-0/+8
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-071-0/+6
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-041-2/+30
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-0/+1
* Code refactoring, no functionality changes.Evan Cheng2010-06-101-1/+4
* Allow targets more controls on what nodes are scheduled by reg pressure, what...Evan Cheng2010-05-201-12/+1
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-201-0/+9
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-2/+1
* Three changes:Chris Lattner2010-04-071-1/+2
* Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may ...Evan Cheng2010-01-221-0/+4
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+1
* Create a new InstrEmitter class for translating SelectionDAG nodesDan Gohman2009-10-101-60/+0
* The ScheduleDAG framework now requires an AliasAnalysis argument, thoughDan Gohman2009-10-091-1/+1
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-8/+3
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ...Evan Cheng2009-09-181-2/+4
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-2/+2
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