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path: root/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
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* Prune Analysis includes from SelectionDAG.hReid Kleckner2019-10-191-1/+2
| | | | | | Only forward declarations are needed here. Follow-on to r375311. llvm-svn: 375319
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* ScheduleDAG: Cleanup dumping code; NFCMatthias Braun2018-09-191-2/+2
| | | | | | | | | | | | - Instead of having both `SUnit::dump(ScheduleDAG*)` and `ScheduleDAG::dumpNode(ScheduleDAG*)`, just keep the latter around. - Add `ScheduleDAG::dump()` and avoid code duplication in several places. Implement it for different ScheduleDAG variants. - Add `ScheduleDAG::dumpNodeName()` in favor of the `SUnit::print()` functions. They were only ever used for debug dumping and putting the function into ScheduleDAG is consistent with the `dumpNode()` change. llvm-svn: 342520
* [CodeGen] Fix inconsistent declaration parameter nameFangrui Song2018-07-161-1/+1
| | | | llvm-svn: 337200
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-1/+1
| | | | | | | | | This is used by llvm tblgen as well as by LLVM Targets, so the only common place is Support for now. (maybe we need another target for these sorts of things - but for now I'm at least making them correct & we can make them better if/when people have strong feelings) llvm-svn: 328395
* [Target] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2017-01-111-3/+16
| | | | | | other minor fixes (NFC). llvm-svn: 291641
* [SelectionDAG] Remove dead code. NFC.Benjamin Kramer2015-10-151-6/+0
| | | | | | Carefully selected parts without deleting graph stuff and dumping methods. llvm-svn: 250434
* Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)Alexander Kornienko2015-06-231-1/+1
| | | | | | Apparently, the style needs to be agreed upon first. llvm-svn: 240390
* Avoid a Symbol -> Name -> Symbol conversion.Rafael Espindola2015-06-221-0/+1
| | | | | | | | | | | | | | Before this we were producing a TargetExternalSymbol from a MCSymbol. That meant extracting the symbol name and fetching the symbol again down the pipeline. This patch adds a DAG.getMCSymbol that lets the MCSymbol pass unchanged on the DAG. Doing so removes the need for MO_NOPREFIX and fixes the root cause of pr23900, allowing r240130 to be committed again. llvm-svn: 240300
* Fixed/added namespace ending comments using clang-tidy. NFCAlexander Kornienko2015-06-191-1/+1
| | | | | | | | | | | | | The patch is generated using this command: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \ -checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \ llvm/lib/ Thanks to Eugene Kosov for the original patch! llvm-svn: 240137
* Use 'override/final' instead of 'virtual' for overridden methodsAlexander Kornienko2015-04-111-1/+1
| | | | | | | | | | | | | | The patch is generated using clang-tidy misc-use-override check. This command was used: tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py \ -checks='-*,misc-use-override' -header-filter='llvm|clang' \ -j=32 -fix -format http://reviews.llvm.org/D8925 llvm-svn: 234679
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-161-1/+1
| | | | | | instead of comparing to nullptr. llvm-svn: 206356
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-081-3/+3
| | | | | | class. llvm-svn: 203339
* Revert "Give internal classes hidden visibility."Benjamin Kramer2013-09-111-1/+1
| | | | | | | It works with clang, but GCC has different rules so we can't make all of those hidden. This reverts commit r190534. llvm-svn: 190536
* Give internal classes hidden visibility.Benjamin Kramer2013-09-111-1/+1
| | | | | | Worth 100k on a linux/x86_64 Release+Asserts clang. llvm-svn: 190534
* Fix #includes, so we include only what we really need.Jakub Staszak2013-02-201-1/+1
| | | | llvm-svn: 175581
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-131-2/+2
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 170140
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-111-2/+2
| | | | llvm-svn: 169854
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-111-2/+2
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 169838
* Add a really faster pre-RA scheduler (-pre-RA-sched=linearize). It doesn't useEvan Cheng2012-10-171-1/+2
| | | | | | | | | | | | | | any scheduling heuristics nor does it build up any scheduling data structure that other heuristics use. It essentially linearize by doing a DFA walk but it does handle glues correctly. IMPORTANT: it probably can't handle all the physical register dependencies so it's not suitable for x86. It also doesn't deal with dbg_value nodes right now so it's definitely is still WIP. rdar://12474515 llvm-svn: 166122
* misched: remove forceUnitLatencies. Defaults are handled by the default ↵Andrew Trick2012-10-081-0/+6
| | | | | | SchedModel llvm-svn: 165417
* Add SelectionDAG::getTargetIndex.Jakob Stoklund Olesen2012-08-071-0/+1
| | | | | | | This adds support for TargetIndex operands during isel. The meaning of these (index, offset, flags) operands is entirely defined by the target. llvm-svn: 161453
* misched: API for minimum vs. expected latency.Andrew Trick2012-06-051-6/+0
| | | | | | | Minimum latency determines per-cycle scheduling groups. Expected latency determines critical path and cost. llvm-svn: 158021
* misched preparation: rename core scheduler methods for consistency.Andrew Trick2012-03-071-6/+6
| | | | | | | We had half the API with one convention, half with another. Now was a good time to clean it up. llvm-svn: 152255
* misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.Andrew Trick2012-03-071-4/+5
| | | | | | | | | | | | | | | | | | | ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation. ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class. ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target. Specific changes: - Removed driver code from ScheduleDAG. clearDAG is the only interface needed. - Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls. - Added ScheduleDAGInstrs::begin()/end() public API. - Moved Sequence into the driver layer, which is specific to the scheduling algorithm. llvm-svn: 152208
* misched preparation: modularize schedule emission.Andrew Trick2012-03-071-0/+8
| | | | | | ScheduleDAG has nothing to do with how the instructions are scheduled. llvm-svn: 152206
* misched preparation: modularize schedule printing.Andrew Trick2012-03-071-0/+2
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152205
* misched preparation: modularize schedule verification.Andrew Trick2012-03-071-0/+4
| | | | | | ScheduleDAG will not refer to the scheduled instruction sequence. llvm-svn: 152204
* Cleanup in preparation for misched: Move DAG visualization logic.Andrew Trick2012-03-071-0/+2
| | | | | | Soon, ScheduleDAG will not refer to the BB. llvm-svn: 152177
* Cleanup: DAG building is specific to either SD or MI scheduling. Not part of ↵Andrew Trick2012-03-071-1/+1
| | | | | | the target interface. llvm-svn: 152174
* Add a RegisterMaskSDNode class.Jakob Stoklund Olesen2012-01-181-0/+1
| | | | | | | | | | | This SelectionDAG node will be attached to call nodes by LowerCall(), and eventually becomes a MO_RegisterMask MachineOperand on the MachineInstr representing the call instruction. LowerCall() will attach a register mask that depends on the calling convention. llvm-svn: 148436
* The index stored in the RegDefIter is one after the current index. When ↵Owen Anderson2011-06-271-1/+1
| | | | | | getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped. llvm-svn: 133923
* Add a new MVT::untyped. This will be used in future work for modelling ISA ↵Owen Anderson2011-06-151-0/+8
| | | | | | features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. llvm-svn: 133106
* Added a check in the preRA scheduler for potential interference on aAndrew Trick2011-04-071-0/+6
| | | | | | | | | induction variable. The preRA scheduler is unaware of induction vars, so we look for potential "virtual register cycles" instead. Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing llvm-svn: 129100
* Introducing a new method of tracking register pressure. We can'tAndrew Trick2011-02-041-2/+30
| | | | | | | | | | | | | | | precisely track pressure on a selection DAG, but we can at least keep it balanced. This design accounts for various interesting aspects of selection DAGS: register and subregister copies, glued nodes, dead nodes, unused registers, etc. Added SUnit::NumRegDefsLeft and ScheduleDAGSDNodes::RegDefIter. Note: I disabled PrescheduleNodesWithMultipleUses when register pressure is enabled, based on no evidence other than I don't think it makes sense to have both enabled. llvm-svn: 124853
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-0/+1
| | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. llvm-svn: 113570
* Code refactoring, no functionality changes.Evan Cheng2010-06-101-1/+4
| | | | llvm-svn: 105775
* Allow targets more controls on what nodes are scheduled by reg pressure, ↵Evan Cheng2010-05-201-12/+1
| | | | | | what for latency in hybrid mode. llvm-svn: 104293
* Add a hybrid bottom up scheduler that reduce register usage while avoidingEvan Cheng2010-05-201-0/+9
| | | | | | | | | pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot of long latency instructions so a strict register pressure reduction scheduler does not work well. Early experiments show this speeds up some NEON loops by over 30%. llvm-svn: 104216
* Get rid of the EdgeMapping map. Instead, just check for BasicBlockDan Gohman2010-05-011-2/+1
| | | | | | changes before doing phi lowering for switches. llvm-svn: 102809
* Three changes:Chris Lattner2010-04-071-1/+2
| | | | | | | | | | | | | | | 1. Introduce some enums and accessors in the InlineAsm class that eliminate a ton of magic numbers when handling inline asm SDNode. 2. Add a new MDNodeSDNode selection dag node type that holds a MDNode (shocking!) 3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc metadata, propagating it to the instruction emitter, which drops it. No functionality change. llvm-svn: 100605
* Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may ↵Evan Cheng2010-01-221-0/+4
| | | | | | improve cache locality. This is controlled by -cluster-loads for now. llvm-svn: 94148
* Initial target-independent CodeGen support for BlockAddresses.Dan Gohman2009-10-301-0/+1
| | | | llvm-svn: 85556
* Create a new InstrEmitter class for translating SelectionDAG nodesDan Gohman2009-10-101-60/+0
| | | | | | | | into MachineInstrs. This is mostly just moving the code from ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr emitting from scheduling. llvm-svn: 83699
* The ScheduleDAG framework now requires an AliasAnalysis argument, thoughDan Gohman2009-10-091-1/+1
| | | | | | it isn't needed in the ScheduleDAGSDNodes schedulers. llvm-svn: 83691
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-8/+3
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-2/+4
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-2/+2
| | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. llvm-svn: 68986
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