| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Make sure we correctly set LiveRegGens when a call is unscheduled. <rdar://p... | Eli Friedman | 2011-12-07 | 1 | -1/+8 |
| * | Fix an assertion in the scheduler. PR11386. No testcase included because it... | Eli Friedman | 2011-12-07 | 1 | -3/+2 |
| * | These global variables aren't thread-safe, STATISTIC is. Andy Trick tells me | Nick Lewycky | 2011-12-07 | 1 | -66/+12 |
| * | Rename MVT::untyped to MVT::Untyped to match similar nomenclature. | Owen Anderson | 2011-11-16 | 1 | -2/+2 |
| * | Added custom lowering for load->dec->store sequence in x86 when the EFLAGS re... | Pete Cooper | 2011-11-15 | 1 | -0/+5 |
| * | Use a bigger hammer to fix PR11314 by disabling the "forcing two-address | Evan Cheng | 2011-11-10 | 1 | -1/+5 |
| * | Speculatively revert commit 144124 (djg) in the hope that the 32 bit | Duncan Sands | 2011-11-09 | 1 | -13/+3 |
| * | Add a hack to the scheduler to disable pseudo-two-address dependencies in | Dan Gohman | 2011-11-08 | 1 | -3/+13 |
| * | Reapply r143206, with fixes. Disallow physical register lifetimes | Dan Gohman | 2011-11-03 | 1 | -2/+181 |
| * | Revert r143206, as there are still some failing tests. | Dan Gohman | 2011-10-29 | 1 | -163/+2 |
| * | Reapply r143177 and r143179 (reverting r143188), with scheduler | Dan Gohman | 2011-10-28 | 1 | -2/+163 |
| * | Speculatively disable Dan's commits 143177 and 143179 to see if | Duncan Sands | 2011-10-28 | 1 | -134/+0 |
| * | Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW | Dan Gohman | 2011-10-28 | 1 | -0/+134 |
| * | Change this overloaded use of Sched::Latency to be an overloaded | Dan Gohman | 2011-10-24 | 1 | -4/+4 |
| * | Remove a now dead function, fixing -Wunused-function warnings from | Chandler Carruth | 2011-10-21 | 1 | -20/+0 |
| * | Delete the list-tdrr scheduler. Top-down schedulers are going away | Dan Gohman | 2011-10-20 | 1 | -203/+11 |
| * | PreRA scheduler should avoid cloning compares. | Andrew Trick | 2011-09-01 | 1 | -1/+35 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -20/+20 |
| * | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 2011-06-27 | 1 | -1/+1 |
| * | pre-RA-sched: Cleanup register pressure tracking. | Andrew Trick | 2011-06-27 | 1 | -7/+3 |
| * | Distinguish early clobber output operands from clobbered registers. | Jakob Stoklund Olesen | 2011-06-27 | 1 | -1/+2 |
| * | Fix some trailing issues from my introduction of MVT::untyped and its use for... | Owen Anderson | 2011-06-21 | 1 | -1/+11 |
| * | Remove unused but set variables. | Benjamin Kramer | 2011-06-18 | 1 | -2/+0 |
| * | Add a new MVT::untyped. This will be used in future work for modelling ISA f... | Owen Anderson | 2011-06-15 | 1 | -9/+39 |
| * | Added -stress-sched flag in the Asserts build. | Andrew Trick | 2011-06-15 | 1 | -14/+42 |
| * | Remove a temporary test case probe in CheckForLiveRegDef. | Andrew Trick | 2011-06-08 | 1 | -1/+0 |
| * | Fix a merge bug in preRAsched for handling physreg aliases. | Andrew Trick | 2011-06-07 | 1 | -4/+6 |
| * | Be careful about scheduling nodes above previous calls. It increase usages of | Evan Cheng | 2011-04-26 | 1 | -1/+42 |
| * | Fix typo | Evan Cheng | 2011-04-26 | 1 | -1/+1 |
| * | In the pre-RA scheduler, maintain cmp+br proximity. | Andrew Trick | 2011-04-14 | 1 | -13/+53 |
| * | Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor lat... | Andrew Trick | 2011-04-13 | 1 | -110/+176 |
| * | Revert 129383. It causes some targets to hit a scheduler assert. | Andrew Trick | 2011-04-12 | 1 | -177/+111 |
| * | PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency. | Andrew Trick | 2011-04-12 | 1 | -111/+177 |
| * | Added a check in the preRA scheduler for potential interference on a | Andrew Trick | 2011-04-07 | 1 | -4/+55 |
| * | Fix for -pre-RA-sched=source. | Andrew Trick | 2011-03-25 | 1 | -0/+2 |
| * | Ensure that def-side physreg copies are scheduled above any other uses | Andrew Trick | 2011-03-23 | 1 | -0/+9 |
| * | whitespace | Andrew Trick | 2011-03-23 | 1 | -2/+2 |
| * | Grammar-o. | Eric Christopher | 2011-03-21 | 1 | -1/+1 |
| * | Re-commit 127368 and 127371. They are exonerated. | Evan Cheng | 2011-03-10 | 1 | -5/+11 |
| * | Revert 127368 and 127371 for now. | Evan Cheng | 2011-03-09 | 1 | -11/+5 |
| * | Change the definition of TargetRegisterInfo::getCrossCopyRegClass to be more | Evan Cheng | 2011-03-09 | 1 | -5/+11 |
| * | Fix typo, make helper static. | Benjamin Kramer | 2011-03-09 | 1 | -3/+3 |
| * | Fix some latent bugs if the nodes are unschedulable. We'd gotten away | Eric Christopher | 2011-03-08 | 1 | -1/+6 |
| * | Further improvements to pre-RA-sched=list-ilp. | Andrew Trick | 2011-03-08 | 1 | -17/+62 |
| * | Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo. | Cameron Zwarich | 2011-03-07 | 1 | -1/+1 |
| * | Typo. | Eric Christopher | 2011-03-06 | 1 | -1/+1 |
| * | Disable a couple of experimental heuristics to get the best results from the ... | Andrew Trick | 2011-03-06 | 1 | -2/+2 |
| * | Be explicit with abs(). Visual Studio workaround. | Andrew Trick | 2011-03-05 | 1 | -4/+6 |
| * | Missing comment. | Andrew Trick | 2011-03-05 | 1 | -0/+2 |
| * | Increased the register pressure limit on x86_64 from 8 to 12 | Andrew Trick | 2011-03-05 | 1 | -22/+143 |
