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path: root/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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* Masked gather and scatter intrinsics - enabled codegen for KNL.Elena Demikhovsky2015-05-031-2/+6
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-25/+28
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-28/+25
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-25/+28
* fix typo and 80-col; NFCSanjay Patel2015-03-271-2/+2
* [SDAG] Handle LowerOperation returning its input consistentlyHal Finkel2015-02-241-3/+7
* [SDAG] Use correct alignments on expanded vector trunc-store/ext-loadsHal Finkel2015-02-221-4/+7
* [SDAG] Don't try to use FP_EXTEND/FP_ROUND for int<->fp promotionsHal Finkel2015-02-121-3/+5
* Fixes a bug in vector load legalization that confused bits and bytes.Michael Kuperstein2015-02-041-3/+3
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-1/+2
* Add minnum / maxnum codegenMatt Arsenault2014-10-211-0/+2
* Teach the AArch64 backend about v4f16 and v8f16Oliver Stannard2014-08-271-6/+17
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-311-3/+3
* [x86] Make vector legalization of extloads work more like the "normal"Chandler Carruth2014-07-241-5/+22
* AA metadata refactoring (introduce AAMDNodes)Hal Finkel2014-07-241-5/+5
* [x86,SDAG] Introduce any- and sign-extend-vector-inreg nodes analogousChandler Carruth2014-07-101-0/+66
* Make it possible for ints/floats to return different values from getBooleanCo...Daniel Sanders2014-07-101-3/+3
* [x86] Add a ZERO_EXTEND_VECTOR_INREG DAG node and use it when wideningChandler Carruth2014-07-091-0/+42
* [cleanup] Hoist an if-else chain on ISD opcodes (really designed forChandler Carruth2014-07-021-17/+28
* [cleanup] Remove dead 'break;' statements that I meant to nuke inChandler Carruth2014-07-021-2/+0
* [cleanup] Hoist the promotion dispatch logic into the promote functionChandler Carruth2014-07-021-23/+22
* [cleanup] Nuke the 'VectorOp' bit of the promote method names.Chandler Carruth2014-07-021-9/+9
* [x86] Clean up and modernize the doxygen and API comments for the vectorChandler Carruth2014-07-021-24/+38
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bs...Benjamin Kramer2014-05-191-0/+27
* Convert more SelectionDAG functions to use ArrayRef.Craig Topper2014-04-281-2/+1
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-10/+7
* [VectorLegalizer/X86] Don't unvectorize fp_to_uint for v8f32->v8i16Adam Nemet2014-03-171-7/+41
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-2/+2
* Expand vector bswap in LegalizeVectorOpsHal Finkel2014-02-031-0/+1
* Keep TBAA info when rewriting SelectionDAG loads and storesRichard Sandiford2013-10-281-4/+7
* Remove pointless assertion after r190376Matt Arsenault2013-09-121-2/+0
* Don't use getSetCCResultType for creating a vselectMatt Arsenault2013-09-101-2/+1
* SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()Tom Stellard2013-08-261-3/+3
* SelectionDAG: Make sure stores are always added to the LegalizedNodes listTom Stellard2013-08-211-1/+1
* Add a llvm.copysign intrinsicHal Finkel2013-08-191-0/+1
* Add ISD::FROUND for libm round()Hal Finkel2013-08-071-0/+1
* TargetLowering: Add getVectorIdxTy() function v2Tom Stellard2013-08-051-3/+3
* Remove trailing whitespace from SelectionDAG/*.cppStephen Lin2013-07-081-1/+1
* Introduce getSelect usage and use more getSelectCCMatt Arsenault2013-06-141-5/+5
* Remove double semicolons.Benjamin Kramer2013-05-281-9/+9
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-10/+10
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-2/+3
* Fix vselect when getSetCCResultType returns a different type from the operandsMatt Arsenault2013-05-071-3/+8
* SelectionDAG compile time improvement.Nadav Rotem2013-02-221-0/+19
* Fix PR15267Michael Liao2013-02-201-14/+119
* This patch aims to reduce compile time in LegalizeTypes by using SmallDenseMap,Preston Gurd2013-01-251-1/+1
* When lowering an inreg sext first shift left, then right arithmetically.Benjamin Kramer2013-01-121-3/+3
* PPC: Implement efficient lowering of sign_extend_inreg.Nadav Rotem2013-01-111-1/+25
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-191-2/+2
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-191-2/+2
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