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path: root/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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* Indent properly, no functionality change.Duncan Sands2011-05-091-12/+12
| | | | llvm-svn: 131082
* PR9055: extend the fix to PR4050 (r70179) to apply to zext and anyext.Eli Friedman2011-04-161-2/+2
| | | | | | | Returning a new node makes the code try to replace the old node, which in the included testcase is killed by CSE. llvm-svn: 129650
* Fix another instance of the DAG combiner not using the correct type for the ↵Owen Anderson2011-04-141-3/+5
| | | | | | RHS of a shift. llvm-svn: 129522
* have dag combine zap "store undef", which can be formed during call loweringChris Lattner2011-04-091-2/+8
| | | | | | with undef arguments. llvm-svn: 129185
* Add a RemoveFromWorklist method to DCI. This is needed to do some complicatedCameron Zwarich2011-04-021-0/+4
| | | | | | | | transformations in target-specific DAG combines without causing DAGCombiner to delete the same node twice. If you know of a better way to avoid this (see my next patch for an example), please let me know. llvm-svn: 128758
* Avoid replacing the value of a directly stored load with the stored value if ↵Evan Cheng2011-03-111-2/+1
| | | | | | the load is indexed. rdar://9117613. llvm-svn: 127440
* Can't introduce floating-point immediate constants after legalization.Stuart Hastings2011-03-021-2/+6
| | | | | | Radar 9056407. llvm-svn: 126864
* Fix typos in the comments.Nadav Rotem2011-02-271-4/+7
| | | | llvm-svn: 126565
* Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize ↵Benjamin Kramer2011-02-261-0/+38
| | | | | | | | | | | legalized code for large integer arithmetic. 1. Inform users of ADDEs with two 0 operands that it never sets carry 2. Fold other ADDs or ADDCs into the ADDE if possible It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code. llvm-svn: 126557
* Allow targets to specify a the type of the RHS of a shift parameterized on ↵Owen Anderson2011-02-251-48/+54
| | | | | | the type of the LHS. llvm-svn: 126518
* Enable support for vector sext and trunc:Nadav Rotem2011-02-241-10/+17
| | | | | | | | | | Limit the folding of any_ext and sext into the load operation to scalars. Limit the active-bits trunc optimization to scalars. Document vector trunc and vector sext in LangRef. Similar to commit 126080 (for enabling zext). llvm-svn: 126424
* Fix 9267; Add vector zext support.Nadav Rotem2011-02-201-1/+3
| | | | | | | | The DAGCombiner folds the zext into complex load instructions. This patch prevents this optimization on vectors since none of the supported targets knows how to perform load+vector_zext in one instruction. llvm-svn: 126080
* Swap VT and DebugLoc operands of getExtLoad() for consistency withStuart Hastings2011-02-161-23/+22
| | | | | | other getNode() methods. Radar 9002173. llvm-svn: 125665
* Refactor zero folding slightly. Clean up todo.Eric Christopher2011-02-161-22/+20
| | | | llvm-svn: 125651
* The change for PR9190 wasn't quite right. We need to avoid making theEric Christopher2011-02-161-2/+12
| | | | | | | | | transformation if we can't legally create a build vector of the correct type. Check that we can make the transformation first, and add a TODO to refactor this code with similar cases. Fixes: PR9223 and rdar://9000350 llvm-svn: 125631
* Revisit my fix for PR9028: the issue is that DAGCombine was Chris Lattner2011-02-131-10/+16
| | | | | | | | | generating i8 shift amounts for things like i1024 types. Add an assert in getNode to prevent this from occuring in the future, fix the buggy transformation, revert my previous patch, and document this gotcha in ISDOpcodes.h llvm-svn: 125465
* A fix for 9165.Nadav Rotem2011-02-121-4/+9
| | | | | | | | The DAGCombiner created illegal BUILD_VECTOR operations. The patch added a check that either illegal operations are allowed or that the created operation is legal. llvm-svn: 125435
* SimplifySelectOps can only handle selects with a scalar condition. Add a checkNadav Rotem2011-02-111-0/+3
| | | | | | that the condition is not a vector. llvm-svn: 125398
* Fix #9190Nadav Rotem2011-02-111-1/+1
| | | | | | | | | | | The bug happens when the DAGCombiner attempts to optimize one of the patterns of the SUB opcode. It tries to create a zero of type v2i64. This type is legal on 32bit machines, but the initializer of this vector (i64) is target dependent. Currently, the initializer attempts to create an i64 zero constant, which fails. Added a flag to tell the DAGCombiner to create a legal zero, if we require that the pass would generate legal types. llvm-svn: 125391
* Given a pair of floating point load and store, if there are no other uses ofEvan Cheng2011-02-021-0/+65
| | | | | | | | | | | | | | | | | | | the load, then it may be legal to transform the load and store to integer load and store of the same width. This is done if the target specified the transformation as profitable. e.g. On arm, this can transform: vldr.32 s0, [] vstr.32 s0, [] to ldr r12, [] str r12, [] rdar://8944252 llvm-svn: 124708
* Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.Richard Osborne2011-01-311-2/+2
| | | | llvm-svn: 124587
* Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, ↵Benjamin Kramer2011-01-301-0/+23
| | | | | | | | | | | | | | | | | | c1+c2) when c1 equals the amount of bits that are truncated off. This happens all the time when a smul is promoted to a larger type. On x86-64 we now compile "int test(int x) { return x/10; }" into movslq %edi, %rax imulq $1717986919, %rax, %rax movq %rax, %rcx shrq $63, %rcx sarq $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax" addl %ecx, %eax This fires 96 times in gcc.c on x86-64. llvm-svn: 124559
* Add the missing sub identity "A-(A-B) -> B" to DAGCombine.Benjamin Kramer2011-01-291-0/+3
| | | | | | | | This happens e.g. for code like "X - X%10" where we lower the modulo operation to a series of multiplies and shifts that are then subtracted from X, leading to this missed optimization. llvm-svn: 124532
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-1/+0
| | | | | | and fixes here and there. llvm-svn: 123170
* DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is ↵Benjamin Kramer2010-12-221-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | illegal. The latter usually compiles into smaller code. example code: unsigned foo(unsigned x, unsigned y) { if (x != 0) y--; return y; } before: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] sbbl %eax, %eax ## encoding: [0x19,0xc0] notl %eax ## encoding: [0xf7,0xd0] addl 8(%esp), %eax ## encoding: [0x03,0x44,0x24,0x08] ret ## encoding: [0xc3] after: _foo: ## @foo cmpl $1, 4(%esp) ## encoding: [0x83,0x7c,0x24,0x04,0x01] movl 8(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x08] adcl $-1, %eax ## encoding: [0x83,0xd0,0xff] ret ## encoding: [0xc3] llvm-svn: 122455
* Fix a bug in ReduceLoadWidth that wasn't handling extendingChris Lattner2010-12-221-1/+4
| | | | | | | | | | | | | | | | | | | | | loads properly. We miscompiled the testcase into: _test: ## @test movl $128, (%rdi) movzbl 1(%rdi), %eax ret Now we get a proper: _test: ## @test movl $128, (%rdi) movsbl (%rdi), %eax movzbl %ah, %eax ret This fixes PR8757. llvm-svn: 122392
* more cleanups, move a check for "roundedness" earlier to rejectChris Lattner2010-12-221-14/+20
| | | | | | unhanded cases faster and simplify code. llvm-svn: 122391
* reduce indentation and improve comments, no functionality change.Chris Lattner2010-12-221-51/+53
| | | | llvm-svn: 122389
* Reapply 122353-122355 with fixes. 122354 was wrong;Dale Johannesen2010-12-211-4/+31
| | | | | | | | the shift type was needed one place, the shift count type another. The transform in 123555 had the same problem. llvm-svn: 122366
* Revert 122353-122355 for the moment, they broke stuff.Dale Johannesen2010-12-211-29/+3
| | | | llvm-svn: 122360
* Add a new transform to DAGCombiner.Dale Johannesen2010-12-211-0/+26
| | | | llvm-svn: 122355
* Get the type of a shift from the shift, not from its shiftDale Johannesen2010-12-211-1/+1
| | | | | | | | count operand. These should be the same but apparently are not always, and this is cleaner anyway. This improves the code in an existing test. llvm-svn: 122354
* Shift by the word size is invalid IR; don't create it.Dale Johannesen2010-12-211-2/+2
| | | | llvm-svn: 122353
* fix some typosChris Lattner2010-12-211-2/+1
| | | | llvm-svn: 122349
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-3/+3
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* Cosmetic changes.Dale Johannesen2010-12-201-2/+2
| | | | llvm-svn: 122259
* Fix a DAGCombiner crash when folding binary vector operations with constantBob Wilson2010-12-171-16/+9
| | | | | | | BUILD_VECTOR operands where the element type is not legal. I had previously changed this code to insert TRUNCATE operations, but that was just wrong. llvm-svn: 122102
* Add a transform to DAG Combiner. This improves theDale Johannesen2010-12-171-0/+20
| | | | | | | code for the case where 32-bit divide by constant is turned into 64-bit multiply by constant. 8771012. llvm-svn: 122090
* take care of some todos, transforming [us]mul_lohi into Chris Lattner2010-12-151-2/+46
| | | | | | a wider mul if the wider mul is legal. llvm-svn: 121848
* when transforming a MULHS into a wider MUL, there is no need to SRA theChris Lattner2010-12-151-1/+1
| | | | | | result, the top bits are truncated off anyway, just use SRL. llvm-svn: 121846
* Add a couple dag combines to transform mulhi/mullo into a wider multiplyChris Lattner2010-12-131-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when the wider type is legal. This allows us to compile: define zeroext i16 @test1(i16 zeroext %x) nounwind { entry: %div = udiv i16 %x, 33 ret i16 %div } into: test1: # @test1 movzwl 4(%esp), %eax imull $63551, %eax, %eax # imm = 0xF83F shrl $21, %eax ret instead of: test1: # @test1 movw $-1985, %ax # imm = 0xFFFFFFFFFFFFF83F mulw 4(%esp) andl $65504, %edx # imm = 0xFFE0 movl %edx, %eax shrl $5, %eax ret Implementing rdar://8760399 and example #4 from: http://blog.regehr.org/archives/320 We should implement the same thing for [su]mul_hilo, but I don't have immediate plans to do this. llvm-svn: 121696
* 80-col fixups.Eric Christopher2010-12-091-9/+15
| | | | llvm-svn: 121356
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-071-11/+11
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* Fix a comment typo.Bob Wilson2010-11-281-1/+1
| | | | llvm-svn: 120235
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-105/+105
| | | | llvm-svn: 119990
* Fix thinko: we must turn select(anyext, sext) into sext(select)Duncan Sands2010-11-181-1/+2
| | | | | | not anyext(select). Spotted by Frits van Bommel. llvm-svn: 119739
* The DAGCombiner was threading select over pairs of extending loads evenDuncan Sands2010-11-181-0/+5
| | | | | | | | | | if the extension types were not the same. The result was that if you fed a select with sext and zext loads, as in the testcase, then it would get turned into a zext (or sext) of the select, which is wrong in the cases when it should have been an sext (resp. zext). Reported and diagnosed by Sebastien Deldon. llvm-svn: 119728
* Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shlDan Gohman2010-11-091-0/+1
| | | | | | in order to fold it into a load. llvm-svn: 118471
* Just return undef for invalid masks or elts, and since we're doing that,Eric Christopher2010-11-031-5/+6
| | | | | | just do it earlier too. llvm-svn: 118195
* If we have an undef mask our Elt will be -1 for our access, handleEric Christopher2010-11-031-3/+7
| | | | | | | | this by using an undef as a pointer. Fixes rdar://8625016 llvm-svn: 118164
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