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| author | Chris Lattner <sabre@nondot.org> | 2010-12-15 05:51:39 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2010-12-15 05:51:39 +0000 |
| commit | b86dceea1bf34dd90350792794db190271745116 (patch) | |
| tree | 6254a3b164f0895408da576c0a2c87e840ec884b /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 54979cddda8e59afedbc66f2c3acf6cd8741306f (diff) | |
| download | bcm5719-llvm-b86dceea1bf34dd90350792794db190271745116.tar.gz bcm5719-llvm-b86dceea1bf34dd90350792794db190271745116.zip | |
when transforming a MULHS into a wider MUL, there is no need to SRA the
result, the top bits are truncated off anyway, just use SRL.
llvm-svn: 121846
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 740b29b57a1..6f0c167d852 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1940,7 +1940,7 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) { N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); - N1 = DAG.getNode(ISD::SRA, DL, NewVT, N1, + N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, DAG.getConstant(SimpleSize, getShiftAmountTy())); return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); } |
