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path: root/llvm/lib/CodeGen/RegisterCoalescer.cpp
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* Remove the -disable-cross-class-join option.Jakob Stoklund Olesen2012-04-251-13/+4
| | | | | | | | Cross-class joins have been normal and fully supported for a while now. With TableGen generating the getMatchingSuperRegClass() hook, they are unlikely to cause problems again. llvm-svn: 155552
* Cross-class joining is winning.Jakob Stoklund Olesen2012-04-251-66/+0
| | | | | | | | | | | | Remove the heuristic for disabling cross-class joins. The greedy register allocator can handle the narrow register classes, and when it splits a live range, it can pick a larger register class. Benchmarks were unaffected by this change. <rdar://problem/11302212> llvm-svn: 155551
* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-051-3/+3
| | | | | | static data size. llvm-svn: 152016
* Stop adding <imp-def> operands when coalescing sub-registers.Jakob Stoklund Olesen2012-03-041-16/+0
| | | | | | | We are already setting <undef> flags, and that is good enough. The <imp-def> operands don't mean anything any more. llvm-svn: 152009
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-4/+4
| | | | llvm-svn: 152001
* Don't redundantly copy implicit operands when rematerializing.Lang Hames2012-03-011-4/+9
| | | | | | | While we're at it - don't copy vreg implicit operands while rematerializing. This fixes PR12138. llvm-svn: 151779
* Check regmask interference for -join-physregs.Jakob Stoklund Olesen2012-02-131-0/+8
| | | | llvm-svn: 150404
* RegAlloc superpass: includes phi elimination, coalescing, and scheduling.Andrew Trick2012-02-101-8/+2
| | | | | | | | | | | | | | | | Creates a configurable regalloc pipeline. Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa. When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>. CodeGen transformation passes are never "required" as an analysis ProcessImplicitDefs does not require LiveVariables. We have a plan to massively simplify some of the early passes within the regalloc superpass. llvm-svn: 150226
* Make sure a reserved register has a live interval before merging.Jakob Stoklund Olesen2012-02-061-1/+5
| | | | llvm-svn: 149910
* Drop the REDEF_BY_EC VNInfo flag.Jakob Stoklund Olesen2012-02-041-33/+0
| | | | | | | | | | A live range that has an early clobber tied redef now looks like a normal tied redef, except the early clobber def uses the early clobber slot. This is enough to handle any strange interference problems. llvm-svn: 149769
* Don't store COPY pointers in VNInfo.Jakob Stoklund Olesen2012-02-041-48/+21
| | | | | | | | | | If a value is defined by a COPY, that instuction can easily and cheaply be found by getInstructionFromIndex(VNI->def). This reduces the size of VNInfo from 24 to 16 bytes, and improves llc compile time by 3%. llvm-svn: 149763
* Re-apply the coalescer fix from r149147. Commit r149597 should have fixed ↵Lang Hames2012-02-021-0/+24
| | | | | | the llvm-gcc and clang self-host issues. llvm-svn: 149598
* Remove code that adds live ranges for dead defs. It seems to be breaking things.Lang Hames2012-01-281-24/+0
| | | | llvm-svn: 149163
* Add a "moveInstr" method to LiveIntervals. This can be used to move instructionsLang Hames2012-01-271-0/+25
| | | | | | | | | around within a basic block while maintaining live-intervals. Updated ScheduleTopDownLive in MachineScheduler.cpp to use the moveInstr API when reordering MIs. llvm-svn: 149147
* Backing out ill-considered 'refactor'.Lang Hames2012-01-271-39/+53
| | | | llvm-svn: 149146
* Move some duplicate loops in the coalescer into their own function.Lang Hames2012-01-271-53/+39
| | | | llvm-svn: 149144
* Physreg dead defs should be handled too.Lang Hames2012-01-271-1/+1
| | | | llvm-svn: 149118
* Rewrite instruction operands in AdjustCopiesBackFrom. Fixes PR11861.Lang Hames2012-01-271-4/+6
| | | | llvm-svn: 149097
* copyImplicitOps is redundant here - the loop above already copies these ops.Lang Hames2012-01-231-1/+0
| | | | llvm-svn: 148725
* Fix typo in comment.Lang Hames2012-01-171-1/+1
| | | | llvm-svn: 148268
* Optimize reserved register coalescing.Jakob Stoklund Olesen2012-01-071-0/+25
| | | | | | | | | | | | | | | | | Reserved registers don't have proper live ranges, their LiveInterval simply has a snippet of liveness for each def. Virtual registers with a single value that is a copy of a reserved register (typically %esp) can be coalesced with the reserved register if the live range doesn't overlap any reserved register defs. When coalescing with a reserved register, don't modify the reserved register live range. Just leave it as a bunch of dead defs. This eliminates quadratic coalescer behavior in i386 functions with many function calls. PR11699 llvm-svn: 147726
* Use the 'regalloc' debug tag for most register allocator tracing.Jakob Stoklund Olesen2012-01-071-1/+1
| | | | llvm-svn: 147725
* Reverting r145899 as it breaks clang self-hostingPete Cooper2011-12-081-0/+66
| | | | llvm-svn: 146136
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+3
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+2
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Removed isWinToJoinCrossClass from the register coalescer.Pete Cooper2011-12-061-66/+0
| | | | | | | | The new register allocator is much more able to split back up ranges too constrained by register classes. Fixes <rdar://problem/10466609> llvm-svn: 145899
* Rename SlotIndexes to match how they are used.Jakob Stoklund Olesen2011-11-131-11/+11
| | | | | | | | | | | | | | | | | | | | The old naming scheme (load/use/def/store) can be traced back to an old linear scan article, but the names don't match how slots are actually used. The load and store slots are not needed after the deferred spill code insertion framework was deleted. The use and def slots don't make any sense because we are using half-open intervals as is customary in C code, but the names suggest closed intervals. In reality, these slots were used to distinguish early-clobber defs from normal defs. The new naming scheme also has 4 slots, but the names match how the slots are really used. This is a purely mechanical renaming, but some of the code makes a lot more sense now. llvm-svn: 144503
* Remove unused DstSubIdx argument.Jakob Stoklund Olesen2011-10-051-23/+5
| | | | llvm-svn: 141214
* Also add <def,undef> flags when coalescing sub-registers.Jakob Stoklund Olesen2011-10-051-0/+8
| | | | | | | | RegisterCoalescer can create sub-register defs when it is joining a register with a sub-register. Add <undef> flags to these new sub-register defs where appropriate. llvm-svn: 141138
* Move getCommonSubClass() into TRI.Jakob Stoklund Olesen2011-09-301-2/+2
| | | | | | It will soon need the context. llvm-svn: 140896
* Revert r139782, "RemoveCopyByCommutingDef doesn't need hasPHIKill()."Jakob Stoklund Olesen2011-09-151-8/+8
| | | | | | | | | | It does, after all. RemoveCopyByCommutingDef rewrites the uses of one particular value number in A. It doesn't know how to rewrite phi uses, so there can't be any. llvm-svn: 139787
* RemoveCopyByCommutingDef doesn't need hasPHIKill().Jakob Stoklund Olesen2011-09-151-8/+8
| | | | | | | | | | | Instead, let HasOtherReachingDefs() test for defs in B that overlap any phi-defs in A as well. This test is slightly different, but almost identical. A perfectly precise test would only check those phi-defs in A that are reachable from AValNo. llvm-svn: 139782
* It is safe to remat a value killed by phis.Jakob Stoklund Olesen2011-09-151-3/+1
| | | | | | | | | | | | | The source live range is recomputed using shrinkToUses() which does handle phis correctly. The hasPHIKill() condition was relevant in the old days when ReMaterializeTrivialDef() tried to recompute the live range itself. The shrinkToUses() function will mark the original def as dead when no more uses and phi kills remain. It is then removed by runOnMachineFunction(). llvm-svn: 139781
* [regcoalescing] bug fix for RegistersDefinedFromSameValue.Andrew Trick2011-09-151-2/+5
| | | | | | | An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal. Fixes PR10920 401.bzip2 miscompile with no IV rewrite. llvm-svn: 139765
* Simplify by using isFullCopy().Jakob Stoklund Olesen2011-09-021-3/+1
| | | | llvm-svn: 139019
* Inflate register classes after coalescing.Jakob Stoklund Olesen2011-08-091-2/+35
| | | | | | | | | | | | | | | | | | | | | | | Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
* Rename member variables to follow coding standards.Jakob Stoklund Olesen2011-08-091-198/+198
| | | | | | No functional change. llvm-svn: 137094
* Move the RegisterCoalescer private to its implementation file.Jakob Stoklund Olesen2011-08-091-1/+123
| | | | | | RegisterCoalescer.h still has the CoalescerPair class interface. llvm-svn: 137088
* Refer to the RegisterCoalescer pass by ID.Jakob Stoklund Olesen2011-08-091-4/+2
| | | | | | | A public interface is no longer needed since RegisterCoalescer is not an analysis any more. llvm-svn: 137082
* Eliminate copies of undefined values during coalescing.Jakob Stoklund Olesen2011-07-261-0/+50
| | | | | | | | | | These copies would coalesce easily, but the resulting value would be defined by a deleted instruction. Now we also remove the undefined value number from the destination register. This fixes PR10503. llvm-svn: 136174
* Fix an easy fixme.Rafael Espindola2011-07-031-6/+10
| | | | llvm-svn: 134364
* Use getVNInfoAt.Rafael Espindola2011-07-021-2/+1
| | | | llvm-svn: 134312
* Check the VN of the src register at the two copies, not just theRafael Espindola2011-07-021-1/+6
| | | | | | register number. llvm-svn: 134309
* Disable commit 134216 ("Add 134199 back, but disable the optimization when ↵Duncan Sands2011-07-011-0/+1
| | | | | | | | | the second copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out because gcc built with dragonegg is going into an infinite loop. llvm-svn: 134237
* Avoid DenseMap lookup.Rafael Espindola2011-07-011-6/+8
| | | | llvm-svn: 134231
* Fix off by one error. I misunderstood the comment about killedAt.Rafael Espindola2011-07-011-1/+1
| | | | llvm-svn: 134229
* Check the liveinterval, not the kill flag.Rafael Espindola2011-07-011-7/+10
| | | | llvm-svn: 134228
* Add 134199 back, but disable the optimization when the second copy is a kill.Rafael Espindola2011-07-011-10/+100
| | | | llvm-svn: 134216
* Revert my previous patch while I debug llvm-gcc bootstrap.Rafael Espindola2011-06-301-95/+10
| | | | llvm-svn: 134201
* Don't give up on coalescing A and B when we findRafael Espindola2011-06-301-10/+95
| | | | | | | | | | | | A = X B = X Instead, proceed as if we had found A = X B = A llvm-svn: 134199
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