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authorRafael Espindola <rafael.espindola@gmail.com>2011-07-01 02:35:06 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2011-07-01 02:35:06 +0000
commit59066f0da080f5e8a8d2813e54e72bc87198a553 (patch)
tree4d0e28958884dce32b423a9d1da6aa3251ca72d3 /llvm/lib/CodeGen/RegisterCoalescer.cpp
parent2de1c33f77d7fe8ac9d5476dd77efd65f5c9e90f (diff)
downloadbcm5719-llvm-59066f0da080f5e8a8d2813e54e72bc87198a553.tar.gz
bcm5719-llvm-59066f0da080f5e8a8d2813e54e72bc87198a553.zip
Check the liveinterval, not the kill flag.
llvm-svn: 134228
Diffstat (limited to 'llvm/lib/CodeGen/RegisterCoalescer.cpp')
-rw-r--r--llvm/lib/CodeGen/RegisterCoalescer.cpp17
1 files changed, 10 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 57156cb61aa..76edc08c52a 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -1197,7 +1197,8 @@ static unsigned ComputeUltimateVN(VNInfo *VNI,
// which allows us to coalesce A and B.
// MI is the definition of B. LR is the life range of A that includes
// the slot just before B. If we return true, we add "B = X" to DupCopies.
-static bool RegistersDefinedFromSameValue(const TargetRegisterInfo &tri,
+static bool RegistersDefinedFromSameValue(LiveIntervals &li,
+ const TargetRegisterInfo &tri,
CoalescerPair &CP, MachineInstr *MI,
LiveRange *LR,
SmallVector<MachineInstr*, 8> &DupCopies) {
@@ -1207,14 +1208,16 @@ static bool RegistersDefinedFromSameValue(const TargetRegisterInfo &tri,
if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys())
return false;
+ unsigned Dst = MI->getOperand(0).getReg();
+ unsigned Src = MI->getOperand(1).getReg();
+
// FIXME: If "B = X" kills X, we have to move the kill back to its
// previous use. For now we just avoid the optimization in that case.
- if (MI->getOperand(1).isKill())
+ SlotIndex CopyIdx = li.getInstructionIndex(MI).getNextIndex().getDefIndex();
+ LiveInterval &SrcInt = li.getInterval(Src);
+ if (SrcInt.killedAt(CopyIdx))
return false;
- unsigned Dst = MI->getOperand(0).getReg();
- unsigned Src = MI->getOperand(1).getReg();
-
if (!TargetRegisterInfo::isVirtualRegister(Src) ||
!TargetRegisterInfo::isVirtualRegister(Dst))
return false;
@@ -1332,7 +1335,7 @@ bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
// from the RHS interval, we can use its value #.
MachineInstr *MI = VNI->getCopy();
if (!CP.isCoalescable(MI) &&
- !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+ !RegistersDefinedFromSameValue(*li_, *tri_, CP, MI, lr, DupCopies))
continue;
LHSValsDefinedFromRHS[VNI] = lr->valno;
@@ -1359,7 +1362,7 @@ bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
// from the LHS interval, we can use its value #.
MachineInstr *MI = VNI->getCopy();
if (!CP.isCoalescable(MI) &&
- !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+ !RegistersDefinedFromSameValue(*li_, *tri_, CP, MI, lr, DupCopies))
continue;
RHSValsDefinedFromLHS[VNI] = lr->valno;
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