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path: root/llvm/lib/CodeGen/MachineVerifier.cpp
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* GlobalISel: Verify G_GEPMatt Arsenault2019-02-051-0/+16
* GlobalISel: Fix verifier crashing on non-register operandsMatt Arsenault2019-02-051-1/+6
* GlobalISel: Enforce operand types for constantsMatt Arsenault2019-02-041-0/+23
* GlobalISel: Verify g_selectMatt Arsenault2019-02-041-24/+40
* MachineVerifier: Move verification of G_* instructions to functionMatt Arsenault2019-02-041-100/+117
* GlobalISel: Verify memory size for load/storeMatt Arsenault2019-01-301-4/+9
* GlobalISel: Verify pointer castsMatt Arsenault2019-01-291-0/+44
* GlobalISel: Verify load/store has a pointer inputMatt Arsenault2019-01-271-1/+6
* Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""Amara Emerson2019-01-271-1/+14
* GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANTMatt Arsenault2019-01-221-0/+10
* GlobalISel: Fix out of bounds crashes in verifierMatt Arsenault2019-01-221-3/+8
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* Revert r351584: "GlobalISel: Verify g_zextload and g_sextload"Amara Emerson2019-01-191-14/+1
* GlobalISel: Verify G_BITCASTMatt Arsenault2019-01-181-0/+13
* GlobalISel: Verify G_ICMP/G_FCMP vector typesMatt Arsenault2019-01-181-0/+11
* GlobalISel: Verify g_zextload and g_sextloadMatt Arsenault2019-01-181-1/+14
* [NFC] fix trivial typos in commentsHiroshi Inoue2019-01-091-1/+1
* [MachineVerifier] Include offending register in allocatable live-in error msg.Florian Hahn2019-01-081-0/+6
* [GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.Amara Emerson2018-12-101-0/+26
* [GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECT...Amara Emerson2018-12-051-0/+57
* Fix typo in verifier error messageMatt Arsenault2018-10-231-1/+1
* [machineverifier] Detect PHI's that are preceeded by non-PHI'sDaniel Sanders2018-10-031-3/+11
* [globalisel][verifier] Run the MachineVerifier from IRTranslator onwardsDaniel Sanders2018-10-021-0/+7
* [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defsBjorn Pettersson2018-09-201-21/+11
* MachineVerifier: Fix assert on implicit virtreg useMatt Arsenault2018-08-271-2/+4
* [MachineVerifier] Check if predecessor is jointly dominated by undefsKrzysztof Parzyszek2018-08-161-1/+11
* Remove trailing spaceFangrui Song2018-07-301-2/+2
* [CodeGen] Fix inconsistent declaration parameter nameFangrui Song2018-07-161-3/+3
* [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug propertyMikael Holmen2018-06-211-0/+4
* [WebAssembly] Add Wasm personality and isScopedEHPersonality()Heejin Ahn2018-05-171-1/+1
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-1/+1
* [MachineVerifier][GlobalISel] Verifying generic extends and truncatesRoman Tereshin2018-05-081-0/+52
* [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all v...Roman Tereshin2018-05-071-4/+14
* [MachineVerifier][GlobalISel] NFC, Improving MO printing and refactoring visi...Roman Tereshin2018-05-071-20/+21
* [GlobalISel] Print/Parse FailedISel MachineFunction propertyRoman Tereshin2018-02-281-5/+9
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-7/+3
* [GISel]: Verify COPIES involving generic registers.Aditya Nandakumar2018-02-091-0/+30
* [MachineVerifier] Add check that renamable operands aren't reserved registers.Geoff Berry2018-01-291-6/+8
* LiveStacks: Rename LiveStack.{h|cpp} to LiveStacks.{h|cpp}; NFCMatthias Braun2017-12-181-1/+1
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
* Rename LiveIntervalAnalysis.h to LiveIntervals.hMatthias Braun2017-12-131-1/+1
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-0/+8
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-1/+1
* MachineVerifier: undef phi arg doesn't need to be live-out from predecessorMatthias Braun2017-12-041-1/+2
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-24/+23
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-301-5/+5
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-1/+1
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-6/+6
* MachineVerifier: Improve register operand checksMatthias Braun2017-11-281-78/+81
* MachineVerifier: Improve PHI operand checkingMatthias Braun2017-11-281-28/+54
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