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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-08-27 17:40:09 +0000 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-08-27 17:40:09 +0000 |
commit | 9eb3dda0b21dbf5707539f80be32643b7ddae50a (patch) | |
tree | 886950a4a0341be872115b1515c4afa206cad46e /llvm/lib/CodeGen/MachineVerifier.cpp | |
parent | 937003cf22e48ec07dd7b0e3509e242c91a69cbd (diff) | |
download | bcm5719-llvm-9eb3dda0b21dbf5707539f80be32643b7ddae50a.tar.gz bcm5719-llvm-9eb3dda0b21dbf5707539f80be32643b7ddae50a.zip |
MachineVerifier: Fix assert on implicit virtreg use
If the liveness of a physical register was invalid, this
was attempting to iterate the subregisters of all register
uses of the instruction, which would assert when it
encountered an implicit virtual register operand.
llvm-svn: 340763
Diffstat (limited to 'llvm/lib/CodeGen/MachineVerifier.cpp')
-rw-r--r-- | llvm/lib/CodeGen/MachineVerifier.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index 1c192815ab9..8b274701d2c 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -1533,10 +1533,12 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) { // get a report for its operand. if (Bad) { for (const MachineOperand &MOP : MI->uses()) { - if (!MOP.isReg()) + if (!MOP.isReg() || !MOP.isImplicit()) continue; - if (!MOP.isImplicit()) + + if (!TargetRegisterInfo::isPhysicalRegister(MOP.getReg())) continue; + for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid(); ++SubRegs) { if (*SubRegs == Reg) { |