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path: root/llvm/lib/CodeGen/MachineInstr.cpp
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* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-051-1/+3
* [X86] Fix several places that weren't passing what they though they were to M...Craig Topper2019-06-021-1/+1
* [DebugInfoMetadata] Refactor DIExpression::prepend constants (NFC)Petar Jovanovic2019-05-201-1/+1
* Recommitting r358783 and r358786 "[MS] Emit S_HEAPALLOCSITE debug info" with ...Amy Huang2019-04-241-0/+13
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-2/+2
* Allow unordered loads to be considered invariant in CodeGenPhilip Reames2019-03-191-3/+5
* Allow code motion (and thus folding) for atomic (but unordered) memory operandsPhilip Reames2019-03-141-3/+1
* [NFC] add/modify wrapper function for findRegisterDefOperand().Chen Zheng2019-02-201-1/+1
* Be conservative about unordered accesses for the momentPhilip Reames2019-02-111-1/+3
* Move IR flag handling directly into builder calls for cases translated from I...Michael Berg2019-02-061-11/+18
* [DEBUGINFO] Reposting r352642: Handle restore instructions in LiveDebugValuesWolfgang Pieb2019-02-041-1/+53
* [CodeGen] Be as conservative about atomic accesses as for volatilePhilip Reames2019-02-011-0/+2
* Reverting r352642 - Handle restore instructions in LiveDebugValues - as it's ...Wolfgang Pieb2019-01-301-53/+1
* [DEBUGINFO] Handle restore instructions in LiveDebugValuesWolfgang Pieb2019-01-301-1/+53
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25Vladimir Stefanovic2019-01-171-2/+3
* Fix MachineInstr::findRegisterUseOperandIdx subreg checksStanislav Mekhanoshin2018-11-121-3/+1
* [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal.Carlos Alberto Enciso2018-10-011-0/+10
* [CodeGen] Always print register ties in MI::dump()Francis Visoiu Mistrih2018-09-261-1/+1
* Copy utilities updated and added for MI flagsMichael Berg2018-09-191-0/+36
* [MachineInstr] In addRegisterKilled and addRegisterDead, don't remove operand...Craig Topper2018-09-131-2/+4
* add IR flags to MIMichael Berg2018-09-111-0/+6
* Fix argument type in MachineInstr::hasPropertyInBundleSven van Haastregt2018-09-061-1/+1
* [DWARF] Missing location debug information with -O2.Carlos Alberto Enciso2018-08-301-0/+17
* Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek2018-08-201-7/+14
* [x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth2018-08-161-25/+67
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-55/+161
* [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug propertyMikael Holmen2018-06-211-12/+34
* [NFC] make MIFlag accessor functions consistant with usage modelMichael Berg2018-06-181-1/+1
* [MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()Roman Tereshin2018-06-121-6/+24
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-3/+4
* [DebugInfo] Convert intrinsic llvm.dbg.label to MachineInstr.Shiva Chen2018-05-091-0/+16
* [MachineVerifier][GlobalISel] Checking that generic instrs have LLTs on all v...Roman Tereshin2018-05-071-2/+6
* MachineInst support mapping SDNode fast math flags for support in Back End co...Michael Berg2018-05-031-0/+14
* IWYU for llvm-config.h in llvm, additions.Nico Weber2018-04-301-0/+1
* [CodeGen] Print user-friendly debug locations as MI commentsFrancis Visoiu Mistrih2018-04-241-1/+14
* [CodeGen] Fix printing bundles in MIR outputKrzysztof Parzyszek2018-04-101-3/+5
* [CodeGen] Use MIR syntax for MachineMemOperand printingFrancis Visoiu Mistrih2018-03-141-10/+18
* [AArch64] Keep track of MIFlags in the LoadStoreOptimizerFrancis Visoiu Mistrih2018-03-141-0/+6
* [MIR] Allow frame-setup and frame-destroy on the same instructionFrancis Visoiu Mistrih2018-03-131-1/+1
* The final step to close D41278 [MachineCombiner] Improve debug output (NFC).Andrew V. Tischenko2018-02-261-0/+2
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-5/+1
* Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasic...Francis Visoiu Mistrih2018-02-191-0/+2
* [CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::p...Francis Visoiu Mistrih2018-02-081-2/+0
* [AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regsGeoff Berry2018-01-291-3/+6
* [CodeGen] Unify printing format of debug-location in both MIR and -debugFrancis Visoiu Mistrih2018-01-191-7/+12
* [CodeGen][NFC] Rename IsVerbose to IsStandalone in Machine*::printFrancis Visoiu Mistrih2018-01-181-7/+7
* [CodeGen] Print RegClasses on MI in verbose modeFrancis Visoiu Mistrih2018-01-181-9/+9
* [CodeGen][NFC] Refactor MachineInstr::printFrancis Visoiu Mistrih2018-01-181-21/+45
* [CodeGen] Remove special case of printing subRegIdx from MachineInstr::printFrancis Visoiu Mistrih2018-01-161-3/+0
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