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path: root/llvm/lib/CodeGen/MachineInstr.cpp
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* moveOperands - assert Src/Dst MachineOperands are non-null.Simon Pilgrim2020-01-111-1/+1
* [FPEnv] Invert sense of MIFlag::FPExcept flagUlrich Weigand2020-01-101-2/+2
* [MIR] Fix cyclic dependency of MIR formatterPeng Guo2020-01-101-6/+3
* Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders2020-01-081-8/+11
* Revert "[MIR] Target specific MIR formating and parsing"Nico Weber2020-01-081-11/+8
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-8/+11
* Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders2020-01-081-11/+8
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-8/+11
* [CodeGen] Increase the size of a SmallVectorJay Foad2019-11-151-1/+1
* [MIR] Add MIR parsing for heap alloc site instruction markersAmy Huang2019-11-051-2/+3
* Fix unused variable warning. NFCI.Simon Pilgrim2019-10-291-1/+1
* Recommit "Add a heap alloc site marker field to the ExtraInfo in MachineInstrs"Amy Huang2019-10-281-72/+70
* Revert "Add an instruction marker field to the ExtraInfo in MachineInstrs."Amy Huang2019-10-251-75/+71
* Add an instruction marker field to the ExtraInfo in MachineInstrs.Amy Huang2019-10-251-71/+75
* Prune two MachineInstr.h includes, fix up depsReid Kleckner2019-10-191-3/+7
* Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjointChangpeng Fang2019-09-261-1/+1
* [DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locationsJeremy Morse2019-09-021-1/+15
* [llvm] Migrate llvm::make_unique to std::make_uniqueJonas Devlieghere2019-08-151-1/+1
* CodeGen: Migration to using RegisterMatt Arsenault2019-08-061-29/+29
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-17/+15
* Allow target to handle STRICT floating-point nodesUlrich Weigand2019-06-051-1/+3
* [X86] Fix several places that weren't passing what they though they were to M...Craig Topper2019-06-021-1/+1
* [DebugInfoMetadata] Refactor DIExpression::prepend constants (NFC)Petar Jovanovic2019-05-201-1/+1
* Recommitting r358783 and r358786 "[MS] Emit S_HEAPALLOCSITE debug info" with ...Amy Huang2019-04-241-0/+13
* [CodeGen] Add "const" to MachineInstr::mayAliasBjorn Pettersson2019-04-191-2/+2
* Allow unordered loads to be considered invariant in CodeGenPhilip Reames2019-03-191-3/+5
* Allow code motion (and thus folding) for atomic (but unordered) memory operandsPhilip Reames2019-03-141-3/+1
* [NFC] add/modify wrapper function for findRegisterDefOperand().Chen Zheng2019-02-201-1/+1
* Be conservative about unordered accesses for the momentPhilip Reames2019-02-111-1/+3
* Move IR flag handling directly into builder calls for cases translated from I...Michael Berg2019-02-061-11/+18
* [DEBUGINFO] Reposting r352642: Handle restore instructions in LiveDebugValuesWolfgang Pieb2019-02-041-1/+53
* [CodeGen] Be as conservative about atomic accesses as for volatilePhilip Reames2019-02-011-0/+2
* Reverting r352642 - Handle restore instructions in LiveDebugValues - as it's ...Wolfgang Pieb2019-01-301-53/+1
* [DEBUGINFO] Handle restore instructions in LiveDebugValuesWolfgang Pieb2019-01-301-1/+53
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25Vladimir Stefanovic2019-01-171-2/+3
* Fix MachineInstr::findRegisterUseOperandIdx subreg checksStanislav Mekhanoshin2018-11-121-3/+1
* [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal.Carlos Alberto Enciso2018-10-011-0/+10
* [CodeGen] Always print register ties in MI::dump()Francis Visoiu Mistrih2018-09-261-1/+1
* Copy utilities updated and added for MI flagsMichael Berg2018-09-191-0/+36
* [MachineInstr] In addRegisterKilled and addRegisterDead, don't remove operand...Craig Topper2018-09-131-2/+4
* add IR flags to MIMichael Berg2018-09-111-0/+6
* Fix argument type in MachineInstr::hasPropertyInBundleSven van Haastregt2018-09-061-1/+1
* [DWARF] Missing location debug information with -O2.Carlos Alberto Enciso2018-08-301-0/+17
* Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek2018-08-201-7/+14
* [x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth2018-08-161-25/+67
* [MI] Change the array of `MachineMemOperand` pointers to beChandler Carruth2018-08-161-55/+161
* [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug propertyMikael Holmen2018-06-211-12/+34
* [NFC] make MIFlag accessor functions consistant with usage modelMichael Berg2018-06-181-1/+1
* [MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()Roman Tereshin2018-06-121-6/+24
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