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path: root/llvm/lib/CodeGen/MIRParser
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* [MIR] Allow frame-setup and frame-destroy on the same instructionFrancis Visoiu Mistrih2018-03-131-5/+7
* [GlobalISel] Print/Parse FailedISel MachineFunction propertyRoman Tereshin2018-02-281-0/+2
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-7/+16
* LLParser: add an argument for overriding data layout and do not check alloca ...Yaxun Liu2018-01-301-1/+1
* [MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih2018-01-263-0/+18
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-191-0/+2
* Revert "AArch64: Fix emergency spillslot being out of reach for large callfra...Matthias Braun2018-01-101-2/+0
* AArch64: Fix emergency spillslot being out of reach for large callframesMatthias Braun2018-01-101-0/+2
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-101-1/+1
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-093-0/+5
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-152-13/+13
* [MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih2017-12-153-0/+83
* Remove redundant includes from lib/CodeGen.Michael Zolotukhin2017-12-131-1/+0
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-123-2/+10
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-042-0/+5
* [mir] Print/Parse both MOLoad and MOStore when they occur together.Daniel Sanders2017-11-281-1/+11
* MIRParser: Avoid reading uninitialized memory on generic vregsJustin Bogner2017-11-171-0/+1
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-3/+3
* [AsmPrinterDwarf] Add support for .cfi_restore directiveFrancis Visoiu Mistrih2017-11-023-0/+9
* Add DK_Remark to SMDiagnosticAdam Nemet2017-10-121-0/+3
* MIR: Serialize CaleeSavedInfo Restored flagMatthias Braun2017-09-281-5/+7
* [CodeGen] Fix some Clang-tidy modernize-use-default-member-init and Include W...Eugene Zelenko2017-09-272-11/+17
* [MIParser] Ensure getHexUint doesn't produce APInts with a bitwidth of 0Jessica Paquette2017-09-011-2/+5
* Attempt to fix the BUILD_SHARED_LIBS build after the DIExpression changeReid Kleckner2017-08-231-1/+1
* Parse and print DIExpressions inline to ease IR and MIR testingReid Kleckner2017-08-233-5/+61
* [MIR] Print target-specific constant poolsDiana Picus2017-08-021-0/+4
* Add an ID field to StackObjectsMatt Arsenault2017-07-201-0/+3
* [MIR] Add support for printing and parsing target MMO flagsGeoff Berry2017-07-132-2/+41
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-113-8/+50
* fix trivial typos, NFCHiroshi Inoue2017-06-271-3/+3
* [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko2017-06-062-13/+47
* llc: Add ability to parse mir from stdinMatthias Braun2017-06-061-1/+1
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* CodeGen: Refactor MIR parsingMatthias Braun2017-06-061-57/+79
* MIR: remove explicit "noVRegs" property.Tim Northover2017-05-301-2/+0
* MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun2017-05-051-7/+35
* MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFCMatthias Braun2017-05-011-1/+2
* Revert "[APInt] Fix a few places that use APInt::getRawData to operate within...Renato Golin2017-04-231-1/+2
* [APInt] Fix a few places that use APInt::getRawData to operate within the nor...Craig Topper2017-04-231-2/+1
* MIR: Allow parsing of empty machine functionsJustin Bogner2017-04-111-3/+0
* [MIR] Support Customed Register Mask and CSRsOren Ben Simhon2017-03-192-20/+50
* ARM: avoid clobbering register in v6 jump-table expansion.Tim Northover2017-03-151-0/+2
* MIR: parse & print the atomic parts of a MachineMemOperand.Tim Northover2017-02-131-2/+40
* [MIRParser] Allow generic register specification on operand.Ahmed Bougacha2017-01-201-12/+16
* MIRParser: Allow regclass specification on operandMatthias Braun2017-01-183-8/+83
* [GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet2016-12-221-3/+3
* [MIRParser] Fix a typo in comment and error message.Quentin Colombet2016-12-221-2/+2
* [MIRParser] Non-generic virtual register may have a type.Quentin Colombet2016-12-221-3/+0
* [MIRParser] Add parsing hex literals of arbitrary size as unsigned integersKrzysztof Parzyszek2016-12-161-13/+38
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