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| author | Tim Northover <tnorthover@apple.com> | 2017-03-15 18:38:13 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2017-03-15 18:38:13 +0000 |
| commit | 0d98b03b9f61ba35d24a590c8b4950e69b57a683 (patch) | |
| tree | 6335404180385c47431f4f0809c309944185e75d /llvm/lib/CodeGen/MIRParser | |
| parent | a3bbf96ebac1a8316da8fc73cefa36fdad856bde (diff) | |
| download | bcm5719-llvm-0d98b03b9f61ba35d24a590c8b4950e69b57a683.tar.gz bcm5719-llvm-0d98b03b9f61ba35d24a590c8b4950e69b57a683.zip | |
ARM: avoid clobbering register in v6 jump-table expansion.
If we got unlucky with register allocation and actual constpool placement, we
could end up producing a tTBB_JT with an index that's already been clobbered.
Technically, we might be able to fix this situation up with a MOV, but I think
the constant islands pass is complex enough without having to deal with more
weird edge-cases.
llvm-svn: 297871
Diffstat (limited to 'llvm/lib/CodeGen/MIRParser')
| -rw-r--r-- | llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 0c694c465b6..79189e30ccd 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -332,6 +332,8 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { MF.setAlignment(YamlMF.Alignment); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); + if (YamlMF.NoVRegs) + MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); if (YamlMF.Legalized) MF.getProperties().set(MachineFunctionProperties::Property::Legalized); if (YamlMF.RegBankSelected) |
