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* [ARM] Fix AAPCS regression caused by r211898Oliver Stannard2014-07-181-1/+5
| | | | | | | | | | | | | r211898 introduced a regression where a large struct, which would normally be passed ByVal, was causing padding to be inserted to prevent the backend from using some GPRs, in order to follow the AAPCS. However, the type of the argument was not being set correctly, so the backend cannot align 8-byte aligned struct types on the stack. The fix is to not insert the padding arguments when the argument is being passed ByVal. llvm-svn: 213359
* [PowerPC] ABI support for aligned by-value aggregatesUlrich Weigand2014-07-101-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for respecting the ABI and type alignment of aggregates passed by value. Currently, all aggregates are aligned at 8 bytes in the parameter save area. This is incorrect for two reasons: - Aggregates that need alignment of 16 bytes or more should be aligned at 16 bytes in the parameter save area. This is implemented by using an appropriate "byval align" attribute in the IR. - Aggregates that need alignment beyond 16 bytes need to be dynamically realigned by the caller. This is implemented by setting the Realign flag of the ABIArgInfo::getIndirect call. In addition, when expanding a va_arg call accessing a type that is aligned at 16 bytes in the argument save area (either one of the aggregate types as above, or a vector type which is already aligned at 16 bytes), code needs to align the va_list pointer accordingly. Reviewed by Hal Finkel. llvm-svn: 212743
* [PowerPC] ABI support for non-Altivec vector typesUlrich Weigand2014-07-101-1/+26
| | | | | | | | | | | | | | | | | | | | | This patch adds support for passing arguments of non-Altivec vector type (i.e. defined via attribute ((vector_size (...)))) on powerpc64-linux. While such types are not mentioned in the formal ABI document, this patch implements a calling convention compatible with GCC: - Vectors of size < 16 bytes are passed in a GPR - Vectors of size > 16 bytes are passed via reference Note that vector types with a number of elements that is not a power of 2 are not supported by GCC, so there is no pre-existing ABI to follow. We choose to pass those (of size < 16) as if widened to the next power of two, so they might end up in a vector register or in a GPR. (Sizes > 16 are always passed via reference as well.) Reviewed by Hal Finkel. llvm-svn: 212734
* MS ABI: Fix __fastcall methods that return structsReid Kleckner2014-07-101-1/+9
| | | | | | | | | The sret paramater consumes the register after the implicit 'this' parameter, as with other calling conventions. Fixes PR20278, which turned out to be very easy. llvm-svn: 212669
* Fix 'source-level' hyphenationsAlp Toker2014-07-091-1/+1
| | | | llvm-svn: 212621
* Move misplaced x86_32 ABI codeRichard Sandiford2014-07-081-38/+38
| | | | | | | | | | r184166 added an X86_32 function in the middle of the SystemZ code. The SystemZ port had been added only a couple of weeks earlier and the original patch probably predated that. No behavioral change intended. llvm-svn: 212524
* ARMEB: Fix function result return for composite typesChristian Pirker2014-07-031-0/+4
| | | | | | Reviewed at http://reviews.llvm.org/D4364 llvm-svn: 212261
* [ARM] Fix AAPCS non-compliance caused by very large structsOliver Stannard2014-06-271-3/+6
| | | | | | | | | | | | | | This is a fix to the code in clang which inserts padding arguments to ensure that the ARM backend can emit AAPCS-VFP compliant code. This code needs to track the number of registers which have been allocated in order to do this. When passing a very large struct (>64 bytes) by value, clang emits IR which takes a pointer to the struct, but the backend converts this back to passing the struct in registers and on the stack. The bug was that this was being considered by clang to only use one register, meaning that there were situations in which padding arguments were incorrectly emitted by clang. llvm-svn: 211898
* Correctly Load Mixed FP-GP Variadic Arguments for x86-64.Rafael Espindola2014-06-241-2/+2
| | | | | | | | | | | | | | | | | | | | According to the x86-64 ABI, structures with both floating point and integer members are split between floating-point and general purpose registers, and consecutive 32-bit floats can be packed into a single floating point register. In the case of variadic functions these are stored to memory and the position recorded in the va_list. This was already correctly implemented in llvm.va_start. The problem is that the code in clang for implementing va_arg was reading floating point registers from the wrong location. Patch by Thomas Jablin. Fixes PR20018. llvm-svn: 211626
* [PowerPC] Fix small argument stack slot offset for LEUlrich Weigand2014-06-201-3/+7
| | | | | | | | | | | | | | | | | When small arguments (structures < 8 bytes or "float") are passed in a stack slot in the ppc64 SVR4 ABI, they must reside in the least significant part of that slot. On BE, this means that an offset needs to be added to the stack address of the parameter, but on LE, the least significant part of the slot has the same address as the slot itself. For the most part, this is handled in the LLVM back-end, where I just fixed the LE case in commit r211368. However, there is one piece of the clang front-end that is also aware of these stack-slot offsets: PPC64_SVR4_ABIInfo::EmitVAArg. This patch updates that routine to take endianness into account. llvm-svn: 211370
* StringRefize TargetInfo::getABI()Alp Toker2014-06-071-3/+3
| | | | llvm-svn: 210402
* XCore target: Fix 'typestring' binding qualifier to the array and not the typeRobert Lytton2014-06-051-6/+12
| | | | | | Differential Revision: http://reviews.llvm.org/D3949 llvm-svn: 210250
* AArch64/ARM64: rename ARM64 components to AArch64Tim Northover2014-05-241-20/+20
| | | | | | This keeps Clang consistent with backend naming conventions. llvm-svn: 209579
* AArch64/ARM64: update Clang after AArch64 removal.Tim Northover2014-05-241-219/+2
| | | | | | | | | | | A few (mostly CodeGen) parts of Clang were tightly coupled to the AArch64 backend. Now that it's gone, they will not even compile. I've also deduplicated RUN lines in many of the AArch64 tests. This might improve "make check-all" time noticably: some of those NEON tests were monsters. llvm-svn: 209578
* [C++11] Use 'nullptr'. CodeGen edition.Craig Topper2014-05-211-40/+40
| | | | llvm-svn: 209272
* XCore target: sort typestring enum fields alphabeticallyRobert Lytton2014-05-201-16/+23
| | | | llvm-svn: 209196
* ARM: PCS non-compliance when struct is padded to avoid register/stack split, ↵Oliver Stannard2014-05-191-4/+8
| | | | | | | | | | and requires internal padding When we were padding a struct to avoid splitting it between registers and the stack, we were throwing away the type which the argument should be coerced to. llvm-svn: 209122
* Update for llvm api change.Rafael Espindola2014-05-171-2/+2
| | | | llvm-svn: 209077
* Update for llvm api change.Rafael Espindola2014-05-171-3/+2
| | | | llvm-svn: 209074
* CodeGen: remove MinGW and Cygwin legacy entriesSaleem Abdulrasool2014-05-171-2/+0
| | | | | | | | | These are now treated as environments. Remove references to these enumeration values in order to clean up the unused enumeration entries in LLVM. The target normalisation prior to tool invocation should ensure that the old values continue to function properly. llvm-svn: 209068
* Update for llvm api change.Rafael Espindola2014-05-161-1/+1
| | | | | | | | | | Now that llvm cannot represent alias cycles, we have to diagnose erros just before trying to close the cycle. This degrades the errors a bit. The real solution is what it was before: if we want to provide good errors for these cases, we have to be able to find a clang level decl given a mangled name and produce the error from Sema. llvm-svn: 209008
* Update for llvm API change.Rafael Espindola2014-05-161-3/+3
| | | | llvm-svn: 208984
* Push record return type classification into CGCXXABIReid Kleckner2014-05-131-102/+43
| | | | | | | | | | | | In the Microsoft C++ ABI, instance methods always return records indirectly via the second hidden parameter. This was implemented in X86_32ABIInfo, but not WinX86_64ABIInfo. Rather than exposing a handful of boolean methods in the CGCXXABI interface, we can expose a single method that applies C++ ABI return value classification rules. llvm-svn: 208733
* MS ABI: Pass 'sret' as the second parameter of instance methodsReid Kleckner2014-05-091-6/+14
| | | | | | | | | | | | | | | | | Summary: MSVC always passes 'sret' after 'this', unlike GCC. This required changing a number of places in Clang that assumed the sret parameter was always first in LLVM IR. This fixes win64 MSVC ABI compatibility for methods returning structs. Reviewers: rsmith, majnemer Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D3618 llvm-svn: 208458
* Reapply r208417 (olista01 'ARM: HFAs must be passed in consecutive ↵James Molloy2014-05-091-19/+6
| | | | | | registers'). Bots are now pacified. llvm-svn: 208425
* Revert r208417 (olista01 'ARM: HFAs must be passed in consecutive ↵James Molloy2014-05-091-6/+19
| | | | | | registers'). This is a followon commit from r208413 which broke the LLVM bots. llvm-svn: 208422
* ARM: HFAs must be passed in consecutive registersOliver Stannard2014-05-091-19/+6
| | | | | | | This is the clang counterpart to 208413, which ensures that Homogeneous Floating-point Aggregates are passed in consecutive registers on ARM. llvm-svn: 208417
* Replace virtual with override.Rafael Espindola2014-05-081-2/+2
| | | | llvm-svn: 208324
* [ARM64-BE] Correctly deal with single element HFAs in varargs.James Molloy2014-05-071-2/+4
| | | | | | | Just because the first "if" didn't fire, doesn't mean we can not have an HFA in the "else" clause. llvm-svn: 208216
* ARM: Fix assertion caused by passing bitfield struct using ↵Oliver Stannard2014-05-071-1/+2
| | | | | | | | | | | | ABIArgInfo::getExpandWithPadding In cases where a struct must, according to the AAPCS, not be split between general purpose and floating point registers, we use ABIArgInfo::getExpandWithPadding to add the padding arguments. However, ExpandWithPadding does not work if the struct contains bitfields, so we instead must use ABIArgInfo::getDirect. llvm-svn: 208185
* XCore target: fix initialization bug found by MSan Bot.Robert Lytton2014-05-061-0/+1
| | | | llvm-svn: 208072
* XCore target: Add TypeString meta data to IR output.Robert Lytton2014-05-021-0/+542
| | | | | | | This includes the addition of the virtual function: TargetCodeGenInfo::EmitTargetMD() llvm-svn: 207832
* Remove unused variable that I missed in my rush to fix the botsReid Kleckner2014-05-021-1/+1
| | | | llvm-svn: 207820
* Win64: Use ConvertType instead of checking the MS inheritanceReid Kleckner2014-05-021-12/+5
| | | | | | | | dependent-type-member-pointer.cpp is failing on a win64 bot because -fms-extensions is not enabled. Use ConvertType rather than relying on the inheritance attributes. It's less code, but probably slower. llvm-svn: 207819
* Win64: Pass member pointers larger than 8 bytes by referenceReid Kleckner2014-05-021-6/+23
| | | | | | | | | | | | | The Win64 ABI docs on MSDN say that arguments bigger than 8 bytes are passed by reference. Prior to this change, we were only applying this logic to RecordType arguments. This affects both the Itanium and Microsoft C++ ABIs. Reviewers: majnemer Differential Revision: http://reviews.llvm.org/D3587 llvm-svn: 207817
* [ARM64] Add a missed case label for arm64_be, and enable the aarch64-varargs ↵James Molloy2014-04-231-1/+2
| | | | | | | | test for arm64_be. This ensures that r203917 (cpirker "AArch64_be varargs processing for ARM ABI") is ported to ARM64. llvm-svn: 206961
* ARM64: Do not expand variadic HFA/HVA arguments with the Darwin ABI.Bob Wilson2014-04-211-6/+24
| | | | | | | | | | | Unlike the standard AAPCS64 ABI, variadic arguments are always passed on the stack with the Darwin ABI, and this was not being considered when deciding whether to expand HFA/HVA arguments in a call. An HFA argument with a "float" base type was being expanded into separate "float" arguments, each of which was then extended to a double, resulting in a serious mismatch from what is expected by the va_arg implementation. <rdar://problem/15777067> llvm-svn: 206729
* Fix a comment typo.Bob Wilson2014-04-211-1/+1
| | | | llvm-svn: 206728
* ARM64: make sure the caller is expected to extend in AAPCS.Tim Northover2014-04-181-2/+3
| | | | | | | This is one of those DarwinPCS differences. It'd been caught in arguments, but not return values. llvm-svn: 206594
* ARM64: make sure HFAs on the stack get properly aligned.Tim Northover2014-04-181-7/+8
| | | | | | Another AAPCS bug, part of PR19432. llvm-svn: 206580
* ARM64: remove holes from *all* HFAs on the stack.Tim Northover2014-04-171-13/+15
| | | | | | | | | | My first attempt to make sure HFAs were contiguous was in the block dealing with padding registers, which meant it only triggered on the first stack-based HFA. This should extend it to the rest as well. Another part of PR19432. llvm-svn: 206456
* Replace push_back()s by initializer list for shorter and cleaner code.Eli Bendersky2014-04-151-5/+3
| | | | llvm-svn: 206304
* Add support for CUDA __launch_bounds__ attribute to CodeGen.Eli Bendersky2014-04-151-10/+28
| | | | | | | | | | Sema does have a CUDALaunchBoundsAttr, but CodeGen was doing nothing with it. This change translates CUDALaunchBoundsAttr to maxntidx and minctasm metadata, which NVPTX then translates to the correct PTX directives. Patch by Manjunath Kudlur. llvm-svn: 206302
* ARM64: track alignment padding registers on AAPCS targetsTim Northover2014-04-151-1/+9
| | | | | | | | | | This implements clause C.8 of the AAPCS in the front-end, so that Clang accurately knows when the registers run out and it has to insert padding before the stack objects begin. PR19432. llvm-svn: 206296
* inalloca: Pad the struct *after* inserting each argReid Kleckner2014-04-101-9/+7
| | | | | | | This ensures that the overall struct size will be a multiple of 4, as required by the ABI. llvm-svn: 205981
* ARM64: initial clang support commit.Tim Northover2014-03-291-229/+574
| | | | | | | | | | | This adds Clang support for the ARM64 backend. There are definitely still some rough edges, so please bring up any issues you see with this patch. As with the LLVM commit though, we think it'll be more useful for merging with AArch64 from within the tree. llvm-svn: 205100
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-281-0/+2
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3096 llvm-svn: 205008
* Use the new Windows environment for target detectionSaleem Abdulrasool2014-03-271-6/+12
| | | | | | | | | This follows the LLVM change to canonicalise the Windows target triple spellings. Rather than treating each Windows environment as a single entity, the environments are now modelled properly as an environment. This is a mechanical change to convert the triple use to reflect that change. llvm-svn: 204978
* [C++11] Replacing CGFunctionInfo arg iterators with iterator_range ↵Aaron Ballman2014-03-171-41/+29
| | | | | | arguments(). Updating all of the usages of the iterators with range-based for loops. llvm-svn: 204068
* AArch64_be varargs processing for ARM ABIChristian Pirker2014-03-141-4/+33
| | | | llvm-svn: 203917
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