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authorTim Northover <tnorthover@apple.com>2014-04-18 10:47:44 +0000
committerTim Northover <tnorthover@apple.com>2014-04-18 10:47:44 +0000
commit07f1624aa2f5089c47a2ff6b02a635af899fa91d (patch)
treee4b80be7dacd1e7fd9b4124b48105b19c0e8d27e /clang/lib/CodeGen/TargetInfo.cpp
parente6c821ef4c55dda76cd0da37d7f5aa72d39ccbab (diff)
downloadbcm5719-llvm-07f1624aa2f5089c47a2ff6b02a635af899fa91d.tar.gz
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ARM64: make sure HFAs on the stack get properly aligned.
Another AAPCS bug, part of PR19432. llvm-svn: 206580
Diffstat (limited to 'clang/lib/CodeGen/TargetInfo.cpp')
-rw-r--r--clang/lib/CodeGen/TargetInfo.cpp15
1 files changed, 8 insertions, 7 deletions
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index e9bb3cdb08b..47c5269ec5a 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -3187,13 +3187,14 @@ private:
// Under AAPCS the 64-bit stack slot alignment means we can't pass HAs
// as sequences of floats since they'll get "holes" inserted as
// padding by the back end.
- if (IsHA && AllocatedVFP > NumVFPs && !isDarwinPCS()) {
- uint32_t NumStackSlots = getContext().getTypeSize(it->type);
- NumStackSlots = llvm::RoundUpToAlignment(NumStackSlots, 64) / 64;
-
- llvm::Type *CoerceTy = llvm::ArrayType::get(
- llvm::Type::getDoubleTy(getVMContext()), NumStackSlots);
- it->info = ABIArgInfo::getDirect(CoerceTy);
+ if (IsHA && AllocatedVFP > NumVFPs && !isDarwinPCS() &&
+ getContext().getTypeAlign(it->type) < 64) {
+ uint32_t NumStackSlots = getContext().getTypeSize(it->type);
+ NumStackSlots = llvm::RoundUpToAlignment(NumStackSlots, 64) / 64;
+
+ llvm::Type *CoerceTy = llvm::ArrayType::get(
+ llvm::Type::getDoubleTy(getVMContext()), NumStackSlots);
+ it->info = ABIArgInfo::getDirect(CoerceTy);
}
// If we do not have enough VFP registers for the HA, any VFP registers
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