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authorTim Northover <tnorthover@apple.com>2014-04-17 10:20:38 +0000
committerTim Northover <tnorthover@apple.com>2014-04-17 10:20:38 +0000
commit5ffc092700012081ea0bd816bab56de5efcb9886 (patch)
tree7ef3c4a2ef44513b3f3885b2121cfe13d9978bb3 /clang/lib/CodeGen/TargetInfo.cpp
parent7e107dabd69242534a6b3be0cba200826f650685 (diff)
downloadbcm5719-llvm-5ffc092700012081ea0bd816bab56de5efcb9886.tar.gz
bcm5719-llvm-5ffc092700012081ea0bd816bab56de5efcb9886.zip
ARM64: remove holes from *all* HFAs on the stack.
My first attempt to make sure HFAs were contiguous was in the block dealing with padding registers, which meant it only triggered on the first stack-based HFA. This should extend it to the rest as well. Another part of PR19432. llvm-svn: 206456
Diffstat (limited to 'clang/lib/CodeGen/TargetInfo.cpp')
-rw-r--r--clang/lib/CodeGen/TargetInfo.cpp28
1 files changed, 15 insertions, 13 deletions
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp
index f2a3a9f8919..e9bb3cdb08b 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -3183,26 +3183,28 @@ private:
const unsigned NumGPRs = 8;
it->info = classifyArgumentType(it->type, AllocatedVFP, IsHA,
AllocatedGPR, IsSmallAggr);
+
+ // Under AAPCS the 64-bit stack slot alignment means we can't pass HAs
+ // as sequences of floats since they'll get "holes" inserted as
+ // padding by the back end.
+ if (IsHA && AllocatedVFP > NumVFPs && !isDarwinPCS()) {
+ uint32_t NumStackSlots = getContext().getTypeSize(it->type);
+ NumStackSlots = llvm::RoundUpToAlignment(NumStackSlots, 64) / 64;
+
+ llvm::Type *CoerceTy = llvm::ArrayType::get(
+ llvm::Type::getDoubleTy(getVMContext()), NumStackSlots);
+ it->info = ABIArgInfo::getDirect(CoerceTy);
+ }
+
// If we do not have enough VFP registers for the HA, any VFP registers
// that are unallocated are marked as unavailable. To achieve this, we add
// padding of (NumVFPs - PreAllocation) floats.
if (IsHA && AllocatedVFP > NumVFPs && PreAllocation < NumVFPs) {
llvm::Type *PaddingTy = llvm::ArrayType::get(
llvm::Type::getFloatTy(getVMContext()), NumVFPs - PreAllocation);
- if (isDarwinPCS())
- it->info = ABIArgInfo::getExpandWithPadding(false, PaddingTy);
- else {
- // Under AAPCS the 64-bit stack slot alignment means we can't pass HAs
- // as sequences of floats since they'll get "holes" inserted as
- // padding by the back end.
- uint32_t NumStackSlots = getContext().getTypeSize(it->type);
- NumStackSlots = llvm::RoundUpToAlignment(NumStackSlots, 64) / 64;
-
- llvm::Type *CoerceTy = llvm::ArrayType::get(
- llvm::Type::getDoubleTy(getVMContext()), NumStackSlots);
- it->info = ABIArgInfo::getDirect(CoerceTy, 0, PaddingTy);
- }
+ it->info.setPaddingType(PaddingTy);
}
+
// If we do not have enough GPRs for the small aggregate, any GPR regs
// that are unallocated are marked as unavailable.
if (IsSmallAggr && AllocatedGPR > NumGPRs && PreGPR < NumGPRs) {
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