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author | James Molloy <james.molloy@arm.com> | 2014-05-09 16:17:09 +0000 |
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committer | James Molloy <james.molloy@arm.com> | 2014-05-09 16:17:09 +0000 |
commit | 1aa0d5f3b276ddb57d4d2b213ff19e09d61d631c (patch) | |
tree | 59a34e808bd80620045b89e3b466ba0069bb801d /clang/lib/CodeGen/TargetInfo.cpp | |
parent | fc13db477ae829a01dceaefb11052f86b08938e4 (diff) | |
download | bcm5719-llvm-1aa0d5f3b276ddb57d4d2b213ff19e09d61d631c.tar.gz bcm5719-llvm-1aa0d5f3b276ddb57d4d2b213ff19e09d61d631c.zip |
Revert r208417 (olista01 'ARM: HFAs must be passed in consecutive registers'). This is a followon commit from r208413 which broke the LLVM bots.
llvm-svn: 208422
Diffstat (limited to 'clang/lib/CodeGen/TargetInfo.cpp')
-rw-r--r-- | clang/lib/CodeGen/TargetInfo.cpp | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/clang/lib/CodeGen/TargetInfo.cpp b/clang/lib/CodeGen/TargetInfo.cpp index 64f9e7b544c..d539ffc5177 100644 --- a/clang/lib/CodeGen/TargetInfo.cpp +++ b/clang/lib/CodeGen/TargetInfo.cpp @@ -3796,7 +3796,7 @@ public: private: ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const; - ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic, + ABIArgInfo classifyArgumentType(QualType RetTy, bool &IsHA, bool isVariadic, bool &IsCPRC) const; bool isIllegalVectorType(QualType Ty) const; @@ -3901,10 +3901,22 @@ void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const { for (auto &I : FI.arguments()) { unsigned PreAllocationVFPs = AllocatedVFPs; unsigned PreAllocationGPRs = AllocatedGPRs; + bool IsHA = false; bool IsCPRC = false; // 6.1.2.3 There is one VFP co-processor register class using registers // s0-s15 (d0-d7) for passing arguments. - I.info = classifyArgumentType(I.type, FI.isVariadic(), IsCPRC); + I.info = classifyArgumentType(I.type, IsHA, FI.isVariadic(), IsCPRC); + assert((IsCPRC || !IsHA) && "Homogeneous aggregates must be CPRCs"); + // If we do not have enough VFP registers for the HA, any VFP registers + // that are unallocated are marked as unavailable. To achieve this, we add + // padding of (NumVFPs - PreAllocationVFP) floats. + // Note that IsHA will only be set when using the AAPCS-VFP calling convention, + // and the callee is not variadic. + if (IsHA && AllocatedVFPs > NumVFPs && PreAllocationVFPs < NumVFPs) { + llvm::Type *PaddingTy = llvm::ArrayType::get( + llvm::Type::getFloatTy(getVMContext()), NumVFPs - PreAllocationVFPs); + I.info = ABIArgInfo::getExpandWithPadding(false, PaddingTy); + } // If we have allocated some arguments onto the stack (due to running // out of VFP registers), we cannot split an argument between GPRs and @@ -3918,7 +3930,6 @@ void ARMABIInfo::computeInfo(CGFunctionInfo &FI) const { llvm::Type::getInt32Ty(getVMContext()), NumGPRs - PreAllocationGPRs); I.info = ABIArgInfo::getDirect(nullptr /* type */, 0 /* offset */, PaddingTy); - } } @@ -4102,7 +4113,8 @@ void ARMABIInfo::resetAllocatedRegs(void) const { VFPRegs[i] = 0; } -ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic, +ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool &IsHA, + bool isVariadic, bool &IsCPRC) const { // We update number of allocated VFPs according to // 6.1.2.1 The following argument types are VFP CPRCs: @@ -4214,8 +4226,9 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic, Base->isSpecificBuiltinType(BuiltinType::LongDouble)); markAllocatedVFPs(2, Members * 2); } + IsHA = true; IsCPRC = true; - return ABIArgInfo::getDirect(); + return ABIArgInfo::getExpand(); } } @@ -4229,7 +4242,7 @@ ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty, bool isVariadic, getABIKind() == ARMABIInfo::AAPCS) ABIAlign = std::min(std::max(TyAlign, (uint64_t)4), (uint64_t)8); if (getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(64)) { - // Update Allocated GPRs + // Update Allocated GPRs markAllocatedGPRs(1, 1); return ABIArgInfo::getIndirect(TyAlign, /*ByVal=*/true, /*Realign=*/TyAlign > ABIAlign); |