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* [PowerPC] Treat 'Z' inline asm constraint as a true memory constraintNemanja Ivanovic2020-06-221-1/+2
* Revert "[RISCV] Add Clang frontend support for Bitmanip extension"Scott Egerton2020-01-152-9/+1
* [RISCV] Add Clang frontend support for Bitmanip extensionScott Egerton2020-01-142-1/+9
* [Driver][PowerPC] Move powerpcspe logic from cc1 to DriverFangrui Song2020-01-101-2/+1
* [PowerPC]: Add powerpcspe target triple subarch componentJustin Hibbits2020-01-082-3/+3
* [PowerPC][Triple] Use elfv2 on freebsd>=13 and linux-muslFangrui Song2020-01-071-1/+1
* [Sema][X86] Consider target attribute into the checks in validateOutputSize a...Craig Topper2019-12-232-14/+20
* reland "[DebugInfo] Support to emit debugInfo for extern variables"Yonghong Song2019-12-221-0/+2
* Revert "[DebugInfo] Support to emit debugInfo for extern variables"Reid Kleckner2019-12-221-2/+0
* Add support for the MS qualifiers __ptr32, __ptr64, __sptr, __uptr.Amy Huang2019-12-185-4/+49
* [PS4] Predefine the __SCE__ macro for the x86_64-scei-ps4 tripleWarren Ristow2019-12-121-0/+1
* [DebugInfo] Support to emit debugInfo for extern variablesYonghong Song2019-12-101-0/+2
* Revert "[Sema][X86] Consider target attribute into the checks in validateOutp...Reid Kleckner2019-12-062-20/+14
* [Sema][X86] Consider target attribute into the checks in validateOutputSize a...Craig Topper2019-12-062-14/+20
* Bug 43965 - Value of _MSVC_LANG doesn't match MSVC++ VS2019 /std:c++latest modeSoumi Manna2019-12-041-1/+1
* [Clang] Define Fuchsia C++ABIPetr Hosek2019-12-031-0/+1
* [ARM][AArch64] Complex addition Neon intrinsics for Armv8.3-AVictor Campos2019-12-023-1/+15
* Revert "[ARM] Allocatable Global Register Variables for ARM"Carey Williams2019-11-292-35/+0
* [mips] Check that features required by built-ins are enabledSimon Atanasyan2019-11-291-0/+3
* [PowerPC] Add new Future CPU for PowerPCStefan Pintilie2019-11-212-3/+27
* [ARM] Allocatable Global Register Variables for ARMAnna Welker2019-11-182-0/+35
* Implement target(branch-protection) attribute for AArch64Momchil Velikov2019-11-152-0/+27
* Add 8548 CPU definition and attributesJustin Hibbits2019-11-122-11/+20
* AArch64: add arm64_32 support to Clang.Tim Northover2019-11-122-7/+33
* [mips] Set macros for Octeon+ CPUSimon Atanasyan2019-11-071-2/+5
* [mips] Add `octeon+` to the list of CPUs accepted by the driverSimon Atanasyan2019-11-072-1/+4
* [X86] Add 'fxsr' feature to -march=pentium2 to match X86.td and gcc.Craig Topper2019-11-061-1/+2
* [X86] Add 'mmx' to all CPUs that have a version of 'sse' and weren't already ...Craig Topper2019-11-061-7/+11
* [mips] Set __OCTEON__ macrosSimon Atanasyan2019-11-051-0/+3
* [mips] Fix `__mips_isa_rev` macros value for Octeon CPUSimon Atanasyan2019-11-051-1/+1
* [Hexagon] Handle remaining registers in getRegisterByName()Krzysztof Parzyszek2019-10-291-1/+4
* Prune include of DataLayout.h from include/clang/Basic/TargetInfo.h. NFCBjorn Pettersson2019-10-211-0/+1
* [BPF] do compile-once run-everywhere relocation for bitfieldsYonghong Song2019-10-082-1/+15
* [SystemZ] Support z15 processor nameUlrich Weigand2019-09-201-1/+1
* [ARM] Update clang for removal of vfp2d16 and vfp2d16spEli Friedman2019-09-171-3/+2
* [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctlyKito Cheng2019-09-171-2/+8
* Reland "Change the X86 datalayout to add three address spacesAmy Huang2019-09-102-14/+24
* [ARM] Add support for the s,j,x,N,O inline asm constraintsDavid Candler2019-09-051-5/+88
* Add -m(no)-spe to clangJustin Hibbits2019-09-052-1/+10
* AMDGPU: Add builtins for is_shared/is_privateMatt Arsenault2019-09-051-0/+2
* [RISCV] Correct Logic around ilp32e macrosSam Elliott2019-09-031-2/+3
* [X86] Remove what little support we had for MPXCraig Topper2019-08-292-9/+0
* Revert "Change the X86 datalayout to add three address spaces for 32 bit sign...Vlad Tsyrklevich2019-08-282-24/+14
* Change the X86 datalayout to add three address spaces for 32 bit signed,Amy Huang2019-08-272-14/+24
* [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targ...Sam Elliott2019-08-271-0/+14
* Reland "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-1/+1
* Revert "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-1/+1
* [ARM] push LR before __gnu_mcount_ncJian Cai2019-08-161-1/+1
* [RISCV] Add inline asm constraint A for RISC-VLewis Revill2019-08-161-0/+4
* [AMDGPU] Do not assume a default GCN targetStanislav Mekhanoshin2019-08-141-4/+1
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