summaryrefslogtreecommitdiffstats
path: root/clang/lib/Basic/Targets
Commit message (Collapse)AuthorAgeFilesLines
* [PowerPC] Treat 'Z' inline asm constraint as a true memory constraintNemanja Ivanovic2020-06-221-1/+2
| | | | | | | | | | | | We currently emit incorrect codegen for this constraint because we set it as a constraint that allows registers. This will cause the value to be copied to the stack and that address to be passed as the address. This is not what we want. Fixes: https://bugs.llvm.org/show_bug.cgi?id=42762 Differential revision: https://reviews.llvm.org/D77542 (cherry picked from commit aede24ecaa08db806fb173faf2de9cff95df8cee)
* Revert "[RISCV] Add Clang frontend support for Bitmanip extension"Scott Egerton2020-01-152-9/+1
| | | | This reverts commit 57cf6ee9c84434161088c39a6f8dd2aae14eb12d.
* [RISCV] Add Clang frontend support for Bitmanip extensionScott Egerton2020-01-142-1/+9
| | | | | | | | | | | | | | Summary: This adds the __riscv_bitmanip macro and the 'b' target feature to enable it. Reviewers: asb, simoncook, lewis-revill, PaoloS, lenary Reviewed By: lenary Subscribers: Jim, rbar, johnrusso, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, pzheng, sameer.abuasal, apazos, luismarques, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71553
* [Driver][PowerPC] Move powerpcspe logic from cc1 to DriverFangrui Song2020-01-101-2/+1
| | | | | | | | | Follow-up of D72014. It is more appropriate to use a target feature instead of a SubTypeArch to express the difference. Reviewed By: #powerpc, jhibbits Differential Revision: https://reviews.llvm.org/D72433
* [PowerPC]: Add powerpcspe target triple subarch componentJustin Hibbits2020-01-082-3/+3
| | | | | | | | | | Summary: This allows the use of '-target powerpcspe-unknown-linux-gnu' or 'powerpcspe-unknown-freebsd' to be used, instead of '-target powerpc-unknown-linux-gnu -mspe'. Reviewed By: dim Differential Revision: https://reviews.llvm.org/D72014
* [PowerPC][Triple] Use elfv2 on freebsd>=13 and linux-muslFangrui Song2020-01-071-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Every powerpc64le platform uses elfv2. For powerpc64, the environments "elfv1" and "elfv2" were added for FreeBSD ELFv1->ELFv2 migration in D61950. FreeBSD developers have decided to use OS versions to select ABI, and no one is relying on the environments. Also use elfv2 on powerpc64-linux-musl. Users can always use -mabi=elfv1 and -mabi=elfv2 to override the default ABI. Reviewed By: adalava Differential Revision: https://reviews.llvm.org/D72352
* [Sema][X86] Consider target attribute into the checks in validateOutputSize ↵Craig Topper2019-12-232-14/+20
| | | | | | | | | | | | | and validateInputSize. The validateOutputSize and validateInputSize need to check whether AVX or AVX512 are enabled. But this can be affected by the target attribute so we need to factor that in. This patch moves some of the code from CodeGen to create an appropriate feature map that we can pass to the function. Differential Revision: https://reviews.llvm.org/D68627
* reland "[DebugInfo] Support to emit debugInfo for extern variables"Yonghong Song2019-12-221-0/+2
| | | | | | | | | | | | | Commit d77ae1552fc21a9f3877f3ed7e13d631f517c825 ("[DebugInfo] Support to emit debugInfo for extern variables") added deebugInfo for extern variables for BPF target. The commit is reverted by 891e25b02d760d0de18c7d46947913b3166047e7 as the committed tests using %clang instead of %clang_cc1 causing test failed in certain scenarios as reported by Reid Kleckner. This patch fixed the tests by using %clang_cc1. Differential Revision: https://reviews.llvm.org/D71818
* Revert "[DebugInfo] Support to emit debugInfo for extern variables"Reid Kleckner2019-12-221-2/+0
| | | | | | | This reverts commit d77ae1552fc21a9f3877f3ed7e13d631f517c825. The tests committed along with this change do not pass, and should be changed to use %clang_cc1.
* Add support for the MS qualifiers __ptr32, __ptr64, __sptr, __uptr.Amy Huang2019-12-185-4/+49
| | | | | | | | | | | | | | | | | | | | Summary: This adds parsing of the qualifiers __ptr32, __ptr64, __sptr, and __uptr and lowers them to the corresponding address space pointer for 32-bit and 64-bit pointers. (32/64-bit pointers added in https://reviews.llvm.org/D69639) A large part of this patch is making these pointers ignore the address space when doing things like overloading and casting. https://bugs.llvm.org/show_bug.cgi?id=42359 Reviewers: rnk, rsmith Subscribers: jholewinski, jvesely, nhaehnle, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D71039
* [PS4] Predefine the __SCE__ macro for the x86_64-scei-ps4 tripleWarren Ristow2019-12-121-0/+1
|
* [DebugInfo] Support to emit debugInfo for extern variablesYonghong Song2019-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extern variable usage in BPF is different from traditional pure user space application. Recent discussion in linux bpf mailing list has two use cases where debug info types are required to use extern variables: - extern types are required to have a suitable interface in libbpf (bpf loader) to provide kernel config parameters to bpf programs. https://lore.kernel.org/bpf/CAEf4BzYCNo5GeVGMhp3fhysQ=_axAf=23PtwaZs-yAyafmXC9g@mail.gmail.com/T/#t - extern types are required so kernel bpf verifier can verify program which uses external functions more precisely. This will make later link with actual external function no need to reverify. https://lore.kernel.org/bpf/87eez4odqp.fsf@toke.dk/T/#m8d5c3e87ffe7f2764e02d722cb0d8cbc136880ed This patch added clang support to emit debuginfo for extern variables with a TargetInfo hook to enable it. The debuginfo for the extern variable is emitted only if that extern variable is referenced in the current compilation unit. Currently, only BPF target enables to generate debug info for extern variables. The emission of such debuginfo is disabled for C++ at this moment since BPF only supports a subset of C language. Emission with C++ can be enabled later if an appropriate use case is identified. -fstandalone-debug permits us to see more debuginfo with the cost of bloated binary size. This patch did not add emission of extern variable debug info with -fstandalone-debug. This can be re-evaluated if there is a real need. Differential Revision: https://reviews.llvm.org/D70696
* Revert "[Sema][X86] Consider target attribute into the checks in ↵Reid Kleckner2019-12-062-20/+14
| | | | | | | | | validateOutputSize and validateInputSize." This reverts commit e1578fd2b79fe5af5f80c0c166a8abd0f816c022. It introduces a dependency on Attr.h which I am removing from ASTContext.h.
* [Sema][X86] Consider target attribute into the checks in validateOutputSize ↵Craig Topper2019-12-062-14/+20
| | | | | | | | | | | | | | | | and validateInputSize. The validateOutputSize and validateInputSize need to check whether AVX or AVX512 are enabled. But this can be affected by the target attribute so we need to factor that in. This patch copies some of the code from CodeGen to create an appropriate feature map that we can pass to the function. Probably need some refactoring here to share more code with Codegen. Is there a good place to do that? Also need to support the cpu_specific attribute as well. Differential Revision: https://reviews.llvm.org/D68627
* Bug 43965 - Value of _MSVC_LANG doesn't match MSVC++ VS2019 /std:c++latest modeSoumi Manna2019-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The patch adds correct value of _MSVC_LANG to match with MSVC++ VS2019 /std:c++latest mode. Bugzilla - Bug 43965 https://bugs.llvm.org/show_bug.cgi?id=43965 The value for a MS specific macro differs from Microsoft starting with VS2019 in /std:c++latest mode. -bash-4.2$ cat msvclang.cpp _MSVC_LANG -bash-4.2$ cl /std:c++latest -E msvclang.cpp Microsoft (R) C/C++ Optimizing Compiler Version 19.20.27508.1 for x64 Copyright (C) Microsoft Corporation. All rights reserved. /std:c++latest is provided as a preview of language features from the latest C++ working draft, and we're eager to hear about bugs and suggestions for improvements. However, note that these features are provided as-is without support, and subject to changes or removal as the working draft evolves. See https://go.microsoft.com/fwlink/?linkid=2045807 for details. msvclang.cpp 201705L -bash-4.2$ clang-cl /std:c++latest -E msvclang.cpp 201704L Reviewers: rnk Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D70996
* [Clang] Define Fuchsia C++ABIPetr Hosek2019-12-031-0/+1
| | | | | | | Currently, it is a modified version of the Itanium ABI, with the only change being that constructors and destructors return 'this'. Differential Revision: https://reviews.llvm.org/D70575
* [ARM][AArch64] Complex addition Neon intrinsics for Armv8.3-AVictor Campos2019-12-023-1/+15
| | | | | | | | | | | | | | | | | | | Summary: Add support for vcadd_* family of intrinsics. This set of intrinsics is available in Armv8.3-A. The fp16 versions require the FP16 extension, which has been available (opt-in) since Armv8.2-A. Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D70862
* Revert "[ARM] Allocatable Global Register Variables for ARM"Carey Williams2019-11-292-35/+0
| | | | This reverts commit 2d739f98d8a53e38bf9faa88cdb6b0c2a363fb77.
* [mips] Check that features required by built-ins are enabledSimon Atanasyan2019-11-291-0/+3
| | | | | | | | | | | | Now Clang does not check that features required by built-in functions are enabled. That causes errors in the backend reported in PR44018. This patch fixes this bug by checking that required features are enabled. This should fix PR44018. Differential Revision: https://reviews.llvm.org/D70808
* [PowerPC] Add new Future CPU for PowerPCStefan Pintilie2019-11-212-3/+27
| | | | | | | | | | | This patch will add -mcpu=future into clang for PowerPC. A CPU type is required for work that may possibly be enabled for some future Power CPU. The CPU type future will serve that purpose. This patch introduces no new functionality. It is an incremental patch on top of which Power PC work for some future CPU can be done. Differential Revision: https://reviews.llvm.org/D70262
* [ARM] Allocatable Global Register Variables for ARMAnna Welker2019-11-182-0/+35
| | | | | | | | | | | | Provides support for using r6-r11 as globally scoped register variables. This requires a -ffixed-rN flag in order to reserve rN against general allocation. If for a given GRV declaration the corresponding flag is not found, or the the register in question is the target's FP, we fail with a diagnostic. Differential Revision: https://reviews.llvm.org/D68862
* Implement target(branch-protection) attribute for AArch64Momchil Velikov2019-11-152-0/+27
| | | | | | | | | This patch implements `__attribute__((target("branch-protection=...")))` in a manner, compatible with the analogous GCC feature: https://gcc.gnu.org/onlinedocs/gcc-9.2.0/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes Differential Revision: https://reviews.llvm.org/D68711
* Add 8548 CPU definition and attributesJustin Hibbits2019-11-122-11/+20
| | | | | | | | 8548 CPU is GCC's name for the e500v2, so accept this in clang. The e500v2 doesn't support lwsync, so define __NO_LWSYNC__ for this as well, as GCC does. Differential Revision: https://reviews.llvm.org/D67787
* AArch64: add arm64_32 support to Clang.Tim Northover2019-11-122-7/+33
|
* [mips] Set macros for Octeon+ CPUSimon Atanasyan2019-11-071-2/+5
|
* [mips] Add `octeon+` to the list of CPUs accepted by the driverSimon Atanasyan2019-11-072-1/+4
|
* [X86] Add 'fxsr' feature to -march=pentium2 to match X86.td and gcc.Craig Topper2019-11-061-1/+2
|
* [X86] Add 'mmx' to all CPUs that have a version of 'sse' and weren't already ↵Craig Topper2019-11-061-7/+11
| | | | | | | | | | | | | | enabling '3dnow' All SSE capable CPUs have MMX. 3dnow implicitly enables MMX. We have code that detects if sse is enabled and implicitly enables MMX unless -mno-mmx is passed. So in most cases we were already enabling MMX if march passed a CPU that supported SSE. The exception to this is if you pass -march for a cpu supports SSE and also pass -mno-sse. We should still enable MMX since its part of the CPU capability.
* [mips] Set __OCTEON__ macrosSimon Atanasyan2019-11-051-0/+3
|
* [mips] Fix `__mips_isa_rev` macros value for Octeon CPUSimon Atanasyan2019-11-051-1/+1
|
* [Hexagon] Handle remaining registers in getRegisterByName()Krzysztof Parzyszek2019-10-291-1/+4
| | | | This fixes https://llvm.org/PR43829.
* Prune include of DataLayout.h from include/clang/Basic/TargetInfo.h. NFCBjorn Pettersson2019-10-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Summary: Use a forward declaration of DataLayout instead of including DataLayout.h in clangs TargetInfo.h. This reduces include dependencies toward DataLayout.h (and other headers such as DerivedTypes.h, Type.h that is included by DataLayout.h). Needed to move implemantation of TargetInfo::resetDataLayout from TargetInfo.h to TargetInfo.cpp. Reviewers: rnk Reviewed By: rnk Subscribers: jvesely, nhaehnle, cfe-commits, llvm-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D69262 llvm-svn: 375438
* [BPF] do compile-once run-everywhere relocation for bitfieldsYonghong Song2019-10-082-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A bpf specific clang intrinsic is introduced: u32 __builtin_preserve_field_info(member_access, info_kind) Depending on info_kind, different information will be returned to the program. A relocation is also recorded for this builtin so that bpf loader can patch the instruction on the target host. This clang intrinsic is used to get certain information to facilitate struct/union member relocations. The offset relocation is extended by 4 bytes to include relocation kind. Currently supported relocation kinds are enum { FIELD_BYTE_OFFSET = 0, FIELD_BYTE_SIZE, FIELD_EXISTENCE, FIELD_SIGNEDNESS, FIELD_LSHIFT_U64, FIELD_RSHIFT_U64, }; for __builtin_preserve_field_info. The old access offset relocation is covered by FIELD_BYTE_OFFSET = 0. An example: struct s { int a; int b1:9; int b2:4; }; enum { FIELD_BYTE_OFFSET = 0, FIELD_BYTE_SIZE, FIELD_EXISTENCE, FIELD_SIGNEDNESS, FIELD_LSHIFT_U64, FIELD_RSHIFT_U64, }; void bpf_probe_read(void *, unsigned, const void *); int field_read(struct s *arg) { unsigned long long ull = 0; unsigned offset = __builtin_preserve_field_info(arg->b2, FIELD_BYTE_OFFSET); unsigned size = __builtin_preserve_field_info(arg->b2, FIELD_BYTE_SIZE); #ifdef USE_PROBE_READ bpf_probe_read(&ull, size, (const void *)arg + offset); unsigned lshift = __builtin_preserve_field_info(arg->b2, FIELD_LSHIFT_U64); #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ lshift = lshift + (size << 3) - 64; #endif #else switch(size) { case 1: ull = *(unsigned char *)((void *)arg + offset); break; case 2: ull = *(unsigned short *)((void *)arg + offset); break; case 4: ull = *(unsigned int *)((void *)arg + offset); break; case 8: ull = *(unsigned long long *)((void *)arg + offset); break; } unsigned lshift = __builtin_preserve_field_info(arg->b2, FIELD_LSHIFT_U64); #endif ull <<= lshift; if (__builtin_preserve_field_info(arg->b2, FIELD_SIGNEDNESS)) return (long long)ull >> __builtin_preserve_field_info(arg->b2, FIELD_RSHIFT_U64); return ull >> __builtin_preserve_field_info(arg->b2, FIELD_RSHIFT_U64); } There is a minor overhead for bpf_probe_read() on big endian. The code and relocation generated for field_read where bpf_probe_read() is used to access argument data on little endian mode: r3 = r1 r1 = 0 r1 = 4 <=== relocation (FIELD_BYTE_OFFSET) r3 += r1 r1 = r10 r1 += -8 r2 = 4 <=== relocation (FIELD_BYTE_SIZE) call bpf_probe_read r2 = 51 <=== relocation (FIELD_LSHIFT_U64) r1 = *(u64 *)(r10 - 8) r1 <<= r2 r2 = 60 <=== relocation (FIELD_RSHIFT_U64) r0 = r1 r0 >>= r2 r3 = 1 <=== relocation (FIELD_SIGNEDNESS) if r3 == 0 goto LBB0_2 r1 s>>= r2 r0 = r1 LBB0_2: exit Compare to the above code between relocations FIELD_LSHIFT_U64 and FIELD_LSHIFT_U64, the code with big endian mode has four more instructions. r1 = 41 <=== relocation (FIELD_LSHIFT_U64) r6 += r1 r6 += -64 r6 <<= 32 r6 >>= 32 r1 = *(u64 *)(r10 - 8) r1 <<= r6 r2 = 60 <=== relocation (FIELD_RSHIFT_U64) The code and relocation generated when using direct load. r2 = 0 r3 = 4 r4 = 4 if r4 s> 3 goto LBB0_3 if r4 == 1 goto LBB0_5 if r4 == 2 goto LBB0_6 goto LBB0_9 LBB0_6: # %sw.bb1 r1 += r3 r2 = *(u16 *)(r1 + 0) goto LBB0_9 LBB0_3: # %entry if r4 == 4 goto LBB0_7 if r4 == 8 goto LBB0_8 goto LBB0_9 LBB0_8: # %sw.bb9 r1 += r3 r2 = *(u64 *)(r1 + 0) goto LBB0_9 LBB0_5: # %sw.bb r1 += r3 r2 = *(u8 *)(r1 + 0) goto LBB0_9 LBB0_7: # %sw.bb5 r1 += r3 r2 = *(u32 *)(r1 + 0) LBB0_9: # %sw.epilog r1 = 51 r2 <<= r1 r1 = 60 r0 = r2 r0 >>= r1 r3 = 1 if r3 == 0 goto LBB0_11 r2 s>>= r1 r0 = r2 LBB0_11: # %sw.epilog exit Considering verifier is able to do limited constant propogation following branches. The following is the code actually traversed. r2 = 0 r3 = 4 <=== relocation r4 = 4 <=== relocation if r4 s> 3 goto LBB0_3 LBB0_3: # %entry if r4 == 4 goto LBB0_7 LBB0_7: # %sw.bb5 r1 += r3 r2 = *(u32 *)(r1 + 0) LBB0_9: # %sw.epilog r1 = 51 <=== relocation r2 <<= r1 r1 = 60 <=== relocation r0 = r2 r0 >>= r1 r3 = 1 if r3 == 0 goto LBB0_11 r2 s>>= r1 r0 = r2 LBB0_11: # %sw.epilog exit For native load case, the load size is calculated to be the same as the size of load width LLVM otherwise used to load the value which is then used to extract the bitfield value. Differential Revision: https://reviews.llvm.org/D67980 llvm-svn: 374099
* [SystemZ] Support z15 processor nameUlrich Weigand2019-09-201-1/+1
| | | | | | | | | | The recently announced IBM z15 processor implements the architecture already supported as "arch13" in LLVM. This patch adds support for "z15" as an alternate architecture name for arch13. Corrsponding LLVM support was committed as rev. 372435. llvm-svn: 372436
* [ARM] Update clang for removal of vfp2d16 and vfp2d16spEli Friedman2019-09-171-3/+2
| | | | | | | | Matching fix for https://reviews.llvm.org/D67375 (r372186). Differential Revision: https://reviews.llvm.org/D67467 llvm-svn: 372187
* [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctlyKito Cheng2019-09-171-2/+8
| | | | | | | | | | | | | | RISC-V LLVM was only implement small/medlow code model, so it defined __riscv_cmodel_medlow directly without check. Now, we have medium/medany code model in RISC-V back-end, it should define according the actually code model. Reviewed By: lewis-revill Differential Revision: https://reviews.llvm.org/D67065 llvm-svn: 372078
* Reland "Change the X86 datalayout to add three address spacesAmy Huang2019-09-102-14/+24
| | | | | | | | | | for 32 bit signed, 32 bit unsigned, and 64 bit pointers." This reverts 57076d3199fc2b0af4a3736b7749dd5462cacda5. Original review at https://reviews.llvm.org/D64931. Review for added fix at https://reviews.llvm.org/D66843. llvm-svn: 371568
* [ARM] Add support for the s,j,x,N,O inline asm constraintsDavid Candler2019-09-051-5/+88
| | | | | | | | | | | | | | | | | | | | | | A number of inline assembly constraints are currently supported by LLVM, but rejected as invalid by Clang: Target independent constraints: s: An integer constant, but allowing only relocatable values ARM specific constraints: j: An immediate integer between 0 and 65535 (valid for MOVW) x: A 32, 64, or 128-bit floating-point/SIMD register: s0-s15, d0-d7, or q0-q3 N: An immediate integer between 0 and 31 (Thumb1 only) O: An immediate integer which is a multiple of 4 between -508 and 508. (Thumb1 only) This patch adds support to Clang for the missing constraints along with some checks to ensure that the constraints are used with the correct target and Thumb mode, and that immediates are within valid ranges (at least where possible). The constraints are already implemented in LLVM, but just a couple of minor corrections to checks (V8M Baseline includes MOVW so should work with 'j', 'N' and 'O' shouldn't be valid in Thumb2) so that Clang and LLVM are in line with each other and the documentation. Differential Revision: https://reviews.llvm.org/D65863 Change-Id: I18076619e319bac35fbb60f590c069145c9d9a0a llvm-svn: 371079
* Add -m(no)-spe to clangJustin Hibbits2019-09-052-1/+10
| | | | | | | | | | | | | | Summary: r337347 added support for the Signal Processing Engine (SPE) to LLVM. This follows that up with the clang side. This adds -mspe and -mno-spe, to match GCC. Subscribers: nemanjai, kbarton, cfe-commits Differential Revision: https://reviews.llvm.org/D49754 llvm-svn: 371066
* AMDGPU: Add builtins for is_shared/is_privateMatt Arsenault2019-09-051-0/+2
| | | | llvm-svn: 371010
* [RISCV] Correct Logic around ilp32e macrosSam Elliott2019-09-031-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: GCC seperates the `__riscv_float_abi_*` macros and the `__riscv_abi_rve` macro. If the chosen abi is ilp32e, `gcc -march=rv32i -mabi=ilp32i -E -dM` shows that both `__riscv_float_abi_soft` and `__riscv_abi_rve` are set. This patch corrects the compiler logic around these defines. At the moment, this patch will not change clang's behaviour, because we do not accept the `ilp32e` abi yet. Reviewers: luismarques, asb Reviewed By: luismarques Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D66591 llvm-svn: 370709
* [X86] Remove what little support we had for MPXCraig Topper2019-08-292-9/+0
| | | | | | | | | | | | | | | -Deprecate -mmpx and -mno-mpx command line options -Remove CPUID detection of mpx for -march=native -Remove MPX from all CPUs -Remove MPX preprocessor define I've left the "mpx" string in the backend so we don't fail on old IR, but its not connected to anything. gcc has also deprecated these command line options. https://www.phoronix.com/scan.php?page=news_item&px=GCC-Patch-To-Drop-MPX Differential Revision: https://reviews.llvm.org/D66669 llvm-svn: 370393
* Revert "Change the X86 datalayout to add three address spaces for 32 bit ↵Vlad Tsyrklevich2019-08-282-24/+14
| | | | | | | | | signed," This reverts commit r370083 because it caused check-lld failures on sanitizer-x86_64-linux-fast. llvm-svn: 370142
* Change the X86 datalayout to add three address spaces for 32 bit signed,Amy Huang2019-08-272-14/+24
| | | | | | 32 bit unsigned, and 64 bit pointers. llvm-svn: 370083
* [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 ↵Sam Elliott2019-08-271-0/+14
| | | | | | | | | | | | | | | | | | targets with atomics Summary: This ensures that libcalls aren't generated when the target supports atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics extension is being targeted. This must be done in setMaxAtomicWidth, as this should be done after handleTargetFeatures has been called. Reviewers: jfb, jyknight, wmi, asb Reviewed By: asb Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna, Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D57450 llvm-svn: 370073
* Reland "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-1/+1
| | | | | | | | This relands r369147 with fixes to unit tests. https://reviews.llvm.org/D65019 llvm-svn: 369173
* Revert "[ARM] push LR before __gnu_mcount_nc"Jian Cai2019-08-161-1/+1
| | | | | | This reverts commit f4cf3b959333f62b7a7b2d7771f7010c9d8da388. llvm-svn: 369149
* [ARM] push LR before __gnu_mcount_ncJian Cai2019-08-161-1/+1
| | | | | | | | | Push LR register before calling __gnu_mcount_nc as it expects the value of LR register to be the top value of the stack on ARM32. Differential Revision: https://reviews.llvm.org/D65019 llvm-svn: 369147
* [RISCV] Add inline asm constraint A for RISC-VLewis Revill2019-08-161-0/+4
| | | | | | | | | | | | This allows the constraint A to be used in inline asm for RISC-V, which allows an address held in a register to be used. This patch adds the minimal amount of code required to get operands with the right constraints to compile. Differential Revision: https://reviews.llvm.org/D54295 llvm-svn: 369093
* [AMDGPU] Do not assume a default GCN targetStanislav Mekhanoshin2019-08-141-4/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D66246 llvm-svn: 368917
OpenPOWER on IntegriCloud