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* [X86] Support -march=tigerlakePengfei Wang2019-08-121-0/+10
* Add SVE opaque built-in typesRichard Sandiford2019-08-091-0/+10
* [ARM] Set default alignment to 64bitsDiogo N. Sampaio2019-08-081-1/+2
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-312-0/+7
* [RISCV] Support 'f' Inline Assembly ConstraintSam Elliott2019-07-311-0/+4
* [RISCV] Add support for floating point registers in inlineasmSimon Cook2019-07-311-9/+24
* [Driver] Define _FILE_OFFSET_BITS=64 on SolarisRainer Orth2019-07-301-1/+4
* [AArch64] Disable __ARM_FEATURE_SVE without ACLE.Sander de Smalen2019-07-301-3/+0
* Revert "[ARM] Set default alignment to 64bits"Petr Hosek2019-07-271-2/+1
* [ARM] Set default alignment to 64bitsSimi Pallipurath2019-07-261-1/+2
* Remove CallingConvMethodTypeErich Keane2019-07-252-4/+4
* Test commit. NFC.Sjoerd Meijer2019-07-241-1/+1
* [SVE][Inline-Asm] Add support to specify SVE registers in the clobber listSander de Smalen2019-07-241-2/+11
* [clang, test] Fix Clang :: Headers/max_align.c on 64-bit SPARCRainer Orth2019-07-231-0/+1
* Disallow most calling convention attributes on PS4Sunil Srivastava2019-07-191-0/+4
* [RISCV] Hard float ABI supportAlex Bradbury2019-07-182-6/+13
* Revert "[RISCV] Hard float ABI support" r366450Alex Bradbury2019-07-182-13/+6
* [RISCV] Hard float ABI supportAlex Bradbury2019-07-182-6/+13
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-172-7/+0
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-172-0/+7
* [AArch64] Consistent types and naming for AArch64 target features (NFC)Momchil Velikov2019-07-172-24/+25
* [AArch64] Implement __jcvt intrinsic from Armv8.3-AKyrylo Tkachov2019-07-162-0/+43
* [PowerPC] Support -mabi=ieeelongdouble and -mabi=ibmlongdoubleFangrui Song2019-07-151-1/+3
* Support __seg_fs and __seg_gs on x86JF Bastien2019-07-141-0/+5
* [SystemZ] Add support for new cpu architecture - arch13Ulrich Weigand2019-07-122-2/+6
* [X86][PowerPC] Support -mlong-double-128Fangrui Song2019-07-122-2/+6
* [HIP] Add GPU arch gfx1010, gfx1011, and gfx1012Yaxun Liu2019-07-111-0/+3
* De-templatize non-dependent VS macro logic, NFCReid Kleckner2019-07-096-73/+85
* [AMDGPU] gfx908 clang targetStanislav Mekhanoshin2019-07-092-0/+7
* [ItaniumMangle] Refactor long double/__float128 mangling and fix the mangled ...Fangrui Song2019-07-093-6/+9
* [X86][PPC] Support -mlong-double-64Fangrui Song2019-07-091-20/+7
* [RISCV] Specify registers used for exception handlingAlex Bradbury2019-07-081-0/+9
* [PowerPC] Support constraint code "ww"Fangrui Song2019-07-041-1/+2
* Fix build failure due to missing breakYaxun Liu2019-06-261-0/+2
* [ARM] Support inline assembler constraints for MVE.Simon Tatham2019-06-251-0/+11
* AMDGPU: Fix target builtins for gfx10Matt Arsenault2019-06-221-0/+2
* [RISCV] Mark TLS as supportedLewis Revill2019-06-191-1/+0
* Clang :: Sema/wchar.c has long been failing on Solaris:Rainer Orth2019-06-171-1/+5
* [Targets] Move soft-float-abi filtering to `initFeatureMap`George Burgess IV2019-06-142-14/+25
* [AMDGPU] gfx1011/gfx1012 clang supportStanislav Mekhanoshin2019-06-141-0/+7
* [RISCV] Add inline asm constraints I, J & K for RISC-VLewis Revill2019-06-112-3/+21
* [X86] Attempt to make the Intel core CPU inheritance a little more readable a...Craig Topper2019-06-101-24/+27
* [ARM] Add ACLE feature macros for MVE.David Green2019-06-071-0/+1
* [ARM] Add ACLE feature macros for MVESjoerd Meijer2019-06-072-0/+30
* [ARM] Fix bugs introduced by the fp64/d32 rework.Simon Tatham2019-06-071-4/+16
* [X86] -march=cooperlake (clang)Pengfei Wang2019-06-071-3/+11
* [X86] Add ENQCMD instructionsPengfei Wang2019-06-062-0/+7
* [X86] Add VP2INTERSECT instructionsPengfei Wang2019-05-312-1/+8
* [ARM] Add CLI support for Armv8.1-M and MVESjoerd Meijer2019-05-301-0/+2
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-10/+8
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