summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* [Hexagon] Fix assert with packetizing IMPLICIT_DEF instructionsKrzysztof Parzyszek2018-04-061-1/+5
| | | | | | | | | | | | | | | | | | The compiler is generating packet with the following instructions, which causes an undefined register assert in the verifier. $r0 = IMPLICIT_DEF $r1 = IMPLICIT_DEF S2_storerd_io killed $r29, 0, killed %d0 The problem is that the packetizer is not saving the IMPLICIT_DEF instructions, which are needed when checking if it is legal to add the store instruction. The fix is to add the IMPLICIT_DEF instructions to the CurrentPacketMIs structure. Patch by Brendon Cahoon. llvm-svn: 329439
* [libFuzzer] Print a correct error message when a directory can't beMatt Morehouse2018-04-062-2/+2
| | | | | | | | | | | | | | | | | | | | | opened. Summary: Currently if the directory cannot be opened for a reason other than non-existence (e.g. too many open file descriptors) the error message printed is incredibly confusing. Patch By: Alex Gaynor Reviewers: kcc, morehouse Reviewed By: morehouse Subscribers: delcypher, llvm-commits, Sanitizers Differential Revision: https://reviews.llvm.org/D45322 llvm-svn: 329438
* [Hexagon] Prevent a stall across zero-latency instructions in a packetKrzysztof Parzyszek2018-04-061-15/+16
| | | | | | | | | | Packetizer keeps two zero-latency bound instrctions in the same packet ignoring the stalls on the later instruction. This should not be the case if there is no data dependence. Patch by Sumanth Gundapaneni. llvm-svn: 329437
* [Hexagon] Remove duplicated code, NFCKrzysztof Parzyszek2018-04-061-9/+0
| | | | llvm-svn: 329436
* [CodeGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-0620-76/+79
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: bogner, rnk, MatzeB, RKSimon Reviewed By: rnk Subscribers: JDevlieghere, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D45133 llvm-svn: 329435
* [Hexagon] Handle subregisters when calculating iteration count in HW loopsKrzysztof Parzyszek2018-04-062-0/+31
| | | | llvm-svn: 329434
* fmod: Port from amd_builtinsJan Vesely2018-04-066-12/+196
| | | | | | | | | | | Uses only denormal path for fp32. Passes CTS on carrizo and turks. v2: whitespace fix Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewer: Aaron Watry <awatry@gmail.com> llvm-svn: 329433
* Cleanup Reduction helpers by using ArrayRef(NoneType) constructor. NFCI.Simon Pilgrim2018-04-061-2/+2
| | | | | | Pointed out by @abataev on D45366. llvm-svn: 329431
* [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_doneDmitry Preobrazhensky2018-04-063-3/+22
| | | | | | | | | See bug 36844: https://bugs.llvm.org/show_bug.cgi?id=36844 Differential Revision: https://reviews.llvm.org/D45313 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329430
* [InstCombine] limit nsz: -(X - Y) --> Y - X to hasOneUse()Sanjay Patel2018-04-062-15/+16
| | | | | | | As noted in the post-commit discussion for r329350, we shouldn't generally assume that fsub is the same cost as fneg. llvm-svn: 329429
* [clang-tidy] Sort includes; NFCGeorge Burgess IV2018-04-061-1/+1
| | | | llvm-svn: 329428
* Add additional tests from D45336Simon Pilgrim2018-04-061-0/+30
| | | | llvm-svn: 329427
* [lldb-server] Set a more generous timeout when testing gdbremote.Davide Italiano2018-04-061-1/+1
| | | | | | | One of our downstream bot is struggling under load, but this value should be enough for everyone. llvm-svn: 329426
* Add additional tests from D45366Simon Pilgrim2018-04-061-0/+33
| | | | llvm-svn: 329425
* [X686] Add appropriate ReadAfterLd for the register input to memory forms of ↵Craig Topper2018-04-065-32/+32
| | | | | | ADC/SBB. llvm-svn: 329424
* Revert "Cleanup DWARFCompileUnit and DWARFUnit in preparation for adding ↵Jan Kratochvil2018-04-068-569/+828
| | | | | | | | | | | | | | | | | DWARFTypeUnit" The reverted commit changed DWARFUnit from https://reviews.llvm.org/D40466 and https://reviews.llvm.org/D42892 that was prepared for DWARFPartialUnit and made from it a superclass for DWARFTypeUnit. DWARFUnit's intention was: DWARFUnit->DWARFSomeNameUnit->DWARFCompileUnit DWARFUnit->DWARFSomeNameUnit->DWARFTypeUnit DWARFUnit->DWARFPartialUnit Discussed at: https://reviews.llvm.org/D45170 This reverts commit r329305. llvm-svn: 329423
* [compiler-rt][dfsan][mips] UnXPASS a consistently passing testSimon Dardis2018-04-061-2/+0
| | | | llvm-svn: 329422
* Strip trailing whitespace. NFCI.Simon Pilgrim2018-04-062-14/+14
| | | | llvm-svn: 329421
* [HIP] define __CUDA_ARCH_=1 for amdgcn targetsYaxun Liu2018-04-061-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D45277 llvm-svn: 329420
* [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*Dmitry Preobrazhensky2018-04-063-64/+162
| | | | | | | | | See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840 Differential Revision: https://reviews.llvm.org/D45250 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329419
* [InstCombine] add test for fsub+fneg with extra use; NFCSanjay Patel2018-04-061-0/+15
| | | | llvm-svn: 329418
* [X86] Remove InstRWs for basic arithmetic instructions from Sandy Bridge ↵Craig Topper2018-04-061-64/+4
| | | | | | | | scheduler model. We can get this right through WriteALU and friends now. llvm-svn: 329417
* [X86] Attempt to model basic arithmetic instructions in the ↵Craig Topper2018-04-068-676/+454
| | | | | | | | | | | | | | | | | | | | | Haswell/Broadwell/Skylake scheduler models without InstRWs Summary: This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency. Apparently we were inconsistent about whether the store has latency or not thus the test changes. I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5. Reviewers: RKSimon, andreadb Reviewed By: andreadb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45351 llvm-svn: 329416
* [X86] Add an extra store address cycle to WriteRMW in the Sandy ↵Craig Topper2018-04-065-15/+15
| | | | | | | | Bridge/Broadwell/Haswell/Skylake scheduler model. Even those the address was calculated for the load, its calculated again for the store. llvm-svn: 329415
* [X86] Merge itineraries for CLC, CMC, and STC.Craig Topper2018-04-063-9/+5
| | | | | | These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation. llvm-svn: 329414
* [CostModel][X86] Regenerate bit count cost tests with ↵Simon Pilgrim2018-04-063-447/+1415
| | | | | | update_analyze_test_checks.py llvm-svn: 329413
* [InstCombine] add potential calloc tests and regenerate checks; NFCSanjay Patel2018-04-061-23/+57
| | | | | | | | D45344 is proposing to remove the use restriction that made the calloc transform safe, but it doesn't currently address the problematic example given inD16337. Add a test to make sure that doesn't break. llvm-svn: 329412
* [OPENMP, NVPTX] Fix codegen for the teams reduction.Alexey Bataev2018-04-066-92/+86
| | | | | | | Added NUW flags for all the add|mul|sub operations + replaced sdiv by udiv as we operate on unsigned values only (addresses, converted to integers) llvm-svn: 329411
* [CostModel][X86] Regenerate vector shuffle cost tests with ↵Simon Pilgrim2018-04-065-856/+1288
| | | | | | update_analyze_test_checks.py llvm-svn: 329410
* [GlobalOpt] Fix support for casts in ctors.Mircea Trofin2018-04-062-1/+67
| | | | | | | | | | | | | | | | Summary: Fixing an issue where initializations of globals where constructors use casts were silently translated to 0-initialization. Reviewers: davidxl, evgeny777 Reviewed By: evgeny777 Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45198 llvm-svn: 329409
* [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructionsDmitry Preobrazhensky2018-04-063-0/+56
| | | | | | | | | See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839 Differential Revision: https://reviews.llvm.org/D45249 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329408
* [CostModel][X86] Regenerate bswap/bitreverse cost tests with ↵Simon Pilgrim2018-04-062-160/+442
| | | | | | update_analyze_test_checks.py llvm-svn: 329407
* [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.Pete Couperus2018-04-062-4/+56
| | | | | | | | | Add disassembler support for instructions which writeback STATUS32. https://reviews.llvm.org/D45148 Patch by Yan Luo! (Yan.Luo2@synopsys.com) llvm-svn: 329404
* [llvm-mca] Do not separate iterations with a newline in the timeline view.Andrea Di Biagio2018-04-0610-31/+31
| | | | | | | Also, update a few tests to minimize the diff in D45369. No functional change intended. llvm-svn: 329403
* [CostModel][X86] Regenerate integer extension/truncation cost tests with ↵Simon Pilgrim2018-04-061-167/+336
| | | | | | update_analyze_test_checks.py llvm-svn: 329402
* [CostModel][X86] Regenerate integer division/remainder tests with ↵Simon Pilgrim2018-04-063-367/+673
| | | | | | update_analyze_test_checks.py llvm-svn: 329401
* [CostModel][X86] Regenerate vector shift cost tests with ↵Simon Pilgrim2018-04-063-1229/+4331
| | | | | | update_analyze_test_checks.py llvm-svn: 329400
* Fix typos in clangAlexander Kornienko2018-04-06231-349/+349
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Found via codespell -q 3 -I ../clang-whitelist.txt Where whitelist consists of: archtype cas classs checkk compres definit frome iff inteval ith lod methode nd optin ot pres statics te thru Patch by luzpaz! (This is a subset of D44188 that applies cleanly with a few files that have dubious fixes reverted.) Differential revision: https://reviews.llvm.org/D44188 llvm-svn: 329399
* [CostModel][X86] Regenerate int<->fp cost tests with ↵Simon Pilgrim2018-04-064-763/+798
| | | | | | update_analyze_test_checks.py llvm-svn: 329398
* [AMDGPU][MC][GFX9] Added s_dcache_discard* instructionsDmitry Preobrazhensky2018-04-063-0/+66
| | | | | | | | | See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838 Differential Revision: https://reviews.llvm.org/D45247 Reviewers: artem.tamazov, arsenm, timcorringham llvm-svn: 329397
* [LoopUnroll] Make LoopPeeling respect the AllowPeeling preference.Chad Rosier2018-04-062-10/+17
| | | | | | | | The SimpleLoopUnrollPass isn't suppose to perform loop peeling. Differential Revision: https://reviews.llvm.org/D45334 llvm-svn: 329395
* [Hexagon] Remove default values from lambda parametersKrzysztof Parzyszek2018-04-061-24/+24
| | | | llvm-svn: 329394
* Followup for r329293: Temporarily disable the breaking test on windows.Philip Pfaffe2018-04-061-1/+2
| | | | | | | This test is failing on windows bots. Disable it temporarily to unbreak the windows bots. llvm-svn: 329393
* DWARFVerifier: validate information in name index entriesPavel Labath2018-04-066-11/+385
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This patch add checks to verify that the information in the name index entries is consistent with the debug_info section. Specifically, we check that entries point to valid DIEs, and their names, tags, and compile units match the information in the debug_info sections. These checks are only run if the previous checks did not find any errors in the name index headers. Attempting to proceed with the checks anyway would likely produce a lot of spurious errors and the verification code would need to be very careful to avoid crashing. I also add a couple of more checks to the abbreviation-validation code to verify that some attributes are always present (an index without a DW_IDX_die_offset attribute is fairly useless). The entry verification works only on indexes without any type units - I haven't attempted to extend it to type units, as we don't even have a DWARF v5-compatible type unit generator at the moment. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45323 llvm-svn: 329392
* Allow the creation of human-friendly ASTDumper to arbitrary output streamAlexander Kornienko2018-04-066-12/+20
| | | | | | | | | | | | | | | | | | | | | Summary: `ASTPrinter` allows setting the ouput to any O-Stream, but that printer creates source-code-like syntax (and is also marked with a `FIXME`). The nice, colourful, mostly human-readable `ASTDumper` only works on the standard output, which is not feasible in case a user wants to see the AST of a file through a code navigation/comprehension tool. This small addition of an overload solves generating a nice colourful AST block for the users of a tool I'm working on, [[ http://github.com/Ericsson/CodeCompass | CodeCompass ]], as opposed to having to duplicate the behaviour of definitions that only exist in the anonymous namespace of implementation TUs related to this module. Reviewers: alexfh, klimek, rsmith Reviewed By: alexfh Subscribers: rnkovacs, dkrupp, gsd, xazax.hun, cfe-commits, #clang Tags: #clang Patch by Whisperity! Differential Revision: https://reviews.llvm.org/D45096 llvm-svn: 329391
* [UpdateTestChecks] Add update_analyze_test_checks.py for cost model analysis ↵Simon Pilgrim2018-04-065-1103/+1742
| | | | | | | | | | | | | | generation The script allows the auto-generation of checks for cost model tests to speed up their creation and help improve coverage, which will help a lot with PR36550. If the need arises we can add support for other analyze passes as well, but the cost models was the one I needed to get done - at the moment it just warns that any other analysis mode is unsupported. I've regenerated a couple of x86 test files to show the effect. Differential Revision: https://reviews.llvm.org/D45272 llvm-svn: 329390
* [X86][SandyBridge] Add (V)DPPS memory fold latenciesSimon Pilgrim2018-04-063-5/+19
| | | | | | Noticed this during D44654 llvm-svn: 329389
* [X86][SandyBridge] SBWriteResPair +5cy Memory FoldsSimon Pilgrim2018-04-0623-1348/+1348
| | | | | | | | | | | | As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
* Tweak an assert message in the verifierHans Wennborg2018-04-062-2/+2
| | | | llvm-svn: 329387
* [X86][SkylakeServer] Merge 2 InstRW entries to the same sched group. NFCI.Simon Pilgrim2018-04-061-2/+2
| | | | llvm-svn: 329386
OpenPOWER on IntegriCloud