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authorCraig Topper <craig.topper@intel.com>2018-04-06 17:12:18 +0000
committerCraig Topper <craig.topper@intel.com>2018-04-06 17:12:18 +0000
commitc50570fb4f12bc07fd18930001cf0a6738aae35b (patch)
treec0be73c001f1d05c2518d05e371a87ea9bce5736
parent7ea906459a14c45cf280b50fc00780eb01653950 (diff)
downloadbcm5719-llvm-c50570fb4f12bc07fd18930001cf0a6738aae35b.tar.gz
bcm5719-llvm-c50570fb4f12bc07fd18930001cf0a6738aae35b.zip
[X686] Add appropriate ReadAfterLd for the register input to memory forms of ADC/SBB.
llvm-svn: 329424
Diffstat
-rwxr-xr-xllvm/lib/Target/X86/X86SchedBroadwell.td14
-rw-r--r--llvm/lib/Target/X86/X86SchedHaswell.td8
-rw-r--r--llvm/lib/Target/X86/X86SchedSandyBridge.td10
-rw-r--r--llvm/lib/Target/X86/X86SchedSkylakeClient.td16
-rwxr-xr-xllvm/lib/Target/X86/X86SchedSkylakeServer.td16
5 files changed, 32 insertions, 32 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index efe10e50734..589d8787d96 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -1397,16 +1397,16 @@ def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
- "ADCX(32|64)rm",
- "ADOX(32|64)rm",
- "BT(16|32|64)mi8",
+def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
"RORX(32|64)mi",
"SARX(32|64)rm",
- "SBB(8|16|32|64)rm",
"SHLX(32|64)rm",
"SHRX(32|64)rm")>;
+def: InstRW<[BWWriteResGroup63, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
+ ADCX32rm, ADCX64rm,
+ ADOX32rm, ADOX64rm,
+ SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
let Latency = 6;
@@ -1967,14 +1967,14 @@ def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPo
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mi",
- "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",
"SBB(8|16|32|64)mi",
- "SBB(8|16|32|64)mr",
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
+def: InstRW<[BWWriteResGroup100, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
+ SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
let Latency = 9;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 142a29bb4c1..544bb65ebf3 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -1663,9 +1663,9 @@ def HWWriteResGroup43 : SchedWriteRes<[HWPort23,HWPort06,HWPort0156]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[HWWriteResGroup43], (instregex "ADC(8|16|32|64)rm")>;
def: InstRW<[HWWriteResGroup43], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
-def: InstRW<[HWWriteResGroup43], (instregex "SBB(8|16|32|64)rm")>;
+def: InstRW<[HWWriteResGroup43, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
+ SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def HWWriteResGroup44 : SchedWriteRes<[HWPort4,HWPort6,HWPort237,HWPort0156]> {
let Latency = 3;
@@ -2063,14 +2063,14 @@ def HWWriteResGroup69 : SchedWriteRes<[HWPort4,HWPort23,HWPort237,HWPort06,HWPor
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[HWWriteResGroup69], (instregex "ADC(8|16|32|64)mi",
- "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
"ROL(8|16|32|64)mCL",
"SAR(8|16|32|64)mCL",
"SBB(8|16|32|64)mi",
- "SBB(8|16|32|64)mr",
"SHL(8|16|32|64)mCL",
"SHR(8|16|32|64)mCL")>;
+def: InstRW<[HWWriteResGroup69, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
+ SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
def HWWriteResGroup70 : SchedWriteRes<[HWPort0,HWPort1]> {
let Latency = 4;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 9babb1464aa..00e1441cdd7 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -1297,9 +1297,9 @@ def SBWriteResGroup65 : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
let NumMicroOps = 3;
let ResourceCycles = [1,1,1];
}
-def: InstRW<[SBWriteResGroup65], (instregex "ADC(8|16|32|64)rm",
- "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
- "SBB(8|16|32|64)rm")>;
+def: InstRW<[SBWriteResGroup65], (instregex "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm")>;
+def: InstRW<[SBWriteResGroup65, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
+ SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
let Latency = 7;
@@ -1687,8 +1687,8 @@ def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let NumMicroOps = 6;
let ResourceCycles = [1,2,2,1];
}
-def: InstRW<[SBWriteResGroup99], (instregex "ADC(8|16|32|64)mr",
- "SBB(8|16|32|64)mr")>;
+def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
+ SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 019b95aac4e..9314f85296f 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1420,16 +1420,16 @@ def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKLWriteResGroup74], (instregex "ADC(8|16|32|64)rm",
- "ADCX(32|64)rm",
- "ADOX(32|64)rm",
- "BT(16|32|64)mi8",
+def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
"RORX(32|64)mi",
"SARX(32|64)rm",
- "SBB(8|16|32|64)rm",
"SHLX(32|64)rm",
"SHRX(32|64)rm")>;
+def: InstRW<[SKLWriteResGroup74, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
+ ADCX32rm, ADCX64rm,
+ ADOX32rm, ADOX64rm,
+ SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
let Latency = 6;
@@ -2028,10 +2028,10 @@ def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[SKLWriteResGroup119], (instregex "ADC(8|16|32|64)mi",
- "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
- "SBB(8|16|32|64)mi",
- "SBB(8|16|32|64)mr")>;
+ "SBB(8|16|32|64)mi")>;
+def: InstRW<[SKLWriteResGroup119, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
+ SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
let Latency = 9;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 3939a28265f..fe144000583 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -3049,16 +3049,16 @@ def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[SKXWriteResGroup78], (instregex "ADC(8|16|32|64)rm",
- "ADCX(32|64)rm",
- "ADOX(32|64)rm",
- "BT(16|32|64)mi8",
+def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8",
"CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
"RORX(32|64)mi",
"SARX(32|64)rm",
- "SBB(8|16|32|64)rm",
"SHLX(32|64)rm",
"SHRX(32|64)rm")>;
+def: InstRW<[SKXWriteResGroup78, ReadAfterLd], (instrs ADC8rm, ADC16rm, ADC32rm, ADC64rm,
+ ADCX32rm, ADCX64rm,
+ ADOX32rm, ADOX64rm,
+ SBB8rm, SBB16rm, SBB32rm, SBB64rm)>;
def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
let Latency = 6;
@@ -4367,10 +4367,10 @@ def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06
let ResourceCycles = [1,1,1,2,1];
}
def: InstRW<[SKXWriteResGroup130], (instregex "ADC(8|16|32|64)mi",
- "ADC(8|16|32|64)mr",
"CMPXCHG(8|16|32|64)rm",
- "SBB(8|16|32|64)mi",
- "SBB(8|16|32|64)mr")>;
+ "SBB(8|16|32|64)mi")>;
+def: InstRW<[SKXWriteResGroup130, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
+ SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
let Latency = 8;
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