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-rw-r--r--llvm/test/MC/AArch64/SVE/and-diagnostics.s19
-rw-r--r--llvm/test/MC/AArch64/SVE/and.s80
-rw-r--r--llvm/test/MC/AArch64/SVE/bic-diagnostics.s67
-rw-r--r--llvm/test/MC/AArch64/SVE/bic.s92
-rw-r--r--llvm/test/MC/AArch64/SVE/eon-diagnostics.s52
-rw-r--r--llvm/test/MC/AArch64/SVE/eon.s56
-rw-r--r--llvm/test/MC/AArch64/SVE/eor-diagnostics.s67
-rw-r--r--llvm/test/MC/AArch64/SVE/eor.s92
-rw-r--r--llvm/test/MC/AArch64/SVE/mov-diagnostics.s18
-rw-r--r--llvm/test/MC/AArch64/SVE/mov.s12
-rw-r--r--llvm/test/MC/AArch64/SVE/orn-diagnostics.s52
-rw-r--r--llvm/test/MC/AArch64/SVE/orn.s56
-rw-r--r--llvm/test/MC/AArch64/SVE/orr-diagnostics.s67
-rw-r--r--llvm/test/MC/AArch64/SVE/orr.s94
14 files changed, 800 insertions, 24 deletions
diff --git a/llvm/test/MC/AArch64/SVE/and-diagnostics.s b/llvm/test/MC/AArch64/SVE/and-diagnostics.s
index f2a5ced66b5..b3d1f8ec832 100644
--- a/llvm/test/MC/AArch64/SVE/and-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/and-diagnostics.s
@@ -46,7 +46,22 @@ and z7.d, z8.d, #254
// CHECK-NEXT: and z7.d, z8.d, #254
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
-bic z7.d, z8.d, #254
+and z0.d, p0/m, z1.d, z2.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
-// CHECK-NEXT: bic z7.d, z8.d, #254
+// CHECK-NEXT: and z0.d, p0/m, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+and z21.d, z5.d, z26.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: and z21.d, z5.d, z26.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate out of restricted predicate range
+
+and z0.d, p8/z, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: and z0.d, p8/z, z0.d, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/and.s b/llvm/test/MC/AArch64/SVE/and.s
index b40c6b6928a..7606128fd0c 100644
--- a/llvm/test/MC/AArch64/SVE/and.s
+++ b/llvm/test/MC/AArch64/SVE/and.s
@@ -13,44 +13,80 @@ and z5.b, z5.b, #0xf9
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
-bic z5.b, z5.b, #0x06
-// CHECK-INST: and z5.b, z5.b, #0xf9
-// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
-
and z23.h, z23.h, #0xfff9
// CHECK-INST: and z23.h, z23.h, #0xfff9
// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
-bic z23.h, z23.h, #0x0006
-// CHECK-INST: and z23.h, z23.h, #0xfff9
-// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
-
and z0.s, z0.s, #0xfffffff9
// CHECK-INST: and z0.s, z0.s, #0xfffffff9
// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
-bic z0.s, z0.s, #0x00000006
-// CHECK-INST: and z0.s, z0.s, #0xfffffff9
-// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
-// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
-
and z0.d, z0.d, #0xfffffffffffffff9
// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9
// CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
-bic z0.d, z0.d, #0x0000000000000006
-// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9
-// CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
+and z5.b, z5.b, #0x6
+// CHECK-INST: and z5.b, z5.b, #0x6
+// CHECK-ENCODING: [0x25,0x3e,0x80,0x05]
// CHECK-ERROR: instruction requires: sve
-// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
+// CHECK-UNKNOWN: 25 3e 80 05 <unknown>
+
+and z23.h, z23.h, #0x6
+// CHECK-INST: and z23.h, z23.h, #0x6
+// CHECK-ENCODING: [0x37,0x7c,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 37 7c 80 05 <unknown>
+
+and z0.s, z0.s, #0x6
+// CHECK-INST: and z0.s, z0.s, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 80 05 <unknown>
+
+and z0.d, z0.d, #0x6
+// CHECK-INST: and z0.d, z0.d, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 83 05 <unknown>
+
+and z0.d, z0.d, z0.d
+// CHECK-INST: and z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 20 04 <unknown>
+
+and z23.d, z13.d, z8.d
+// CHECK-INST: and z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x28,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 28 04 <unknown>
+
+and z31.b, p7/m, z31.b, z31.b
+// CHECK-INST: and z31.b, p7/m, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x1f,0x1a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 1a 04 <unknown>
+
+and z31.h, p7/m, z31.h, z31.h
+// CHECK-INST: and z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x1f,0x5a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 5a 04 <unknown>
+
+and z31.s, p7/m, z31.s, z31.s
+// CHECK-INST: and z31.s, p7/m, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x1f,0x9a,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 9a 04 <unknown>
+
+and z31.d, p7/m, z31.d, z31.d
+// CHECK-INST: and z31.d, p7/m, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x1f,0xda,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f da 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/bic-diagnostics.s b/llvm/test/MC/AArch64/SVE/bic-diagnostics.s
new file mode 100644
index 00000000000..e8ab74c3957
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/bic-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate not compatible with encode/decode function.
+
+bic z5.b, z5.b, #0xfa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: bic z5.b, z5.b, #0xfa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z5.b, z5.b, #0xfff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: bic z5.b, z5.b, #0xfff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z5.h, z5.h, #0xfffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: bic z5.h, z5.h, #0xfffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z5.h, z5.h, #0xfffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: bic z5.h, z5.h, #0xfffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z5.s, z5.s, #0xfffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: bic z5.s, z5.s, #0xfffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z5.s, z5.s, #0xffffffffffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: bic z5.s, z5.s, #0xffffffffffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z15.d, z15.d, #0xfffffffffffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: bic z15.d, z15.d, #0xfffffffffffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+bic z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: bic z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+bic z0.d, p0/m, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: bic z0.d, p0/m, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+bic z21.d, z5.d, z26.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: bic z21.d, z5.d, z26.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate out of restricted predicate range
+
+bic z0.d, p8/z, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: bic z0.d, p8/z, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/bic.s b/llvm/test/MC/AArch64/SVE/bic.s
new file mode 100644
index 00000000000..0a26b927a7c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/bic.s
@@ -0,0 +1,92 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+bic z5.b, z5.b, #0xf9
+// CHECK-INST: and z5.b, z5.b, #0x6
+// CHECK-ENCODING: [0x25,0x3e,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 3e 80 05 <unknown>
+
+bic z23.h, z23.h, #0xfff9
+// CHECK-INST: and z23.h, z23.h, #0x6
+// CHECK-ENCODING: [0x37,0x7c,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 37 7c 80 05 <unknown>
+
+bic z0.s, z0.s, #0xfffffff9
+// CHECK-INST: and z0.s, z0.s, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 80 05 <unknown>
+
+bic z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-INST: and z0.d, z0.d, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x83,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 83 05 <unknown>
+
+bic z5.b, z5.b, #0x6
+// CHECK-INST: and z5.b, z5.b, #0xf9
+// CHECK-ENCODING: [0xa5,0x2e,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a5 2e 80 05 <unknown>
+
+bic z23.h, z23.h, #0x6
+// CHECK-INST: and z23.h, z23.h, #0xfff9
+// CHECK-ENCODING: [0xb7,0x6d,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 6d 80 05 <unknown>
+
+bic z0.s, z0.s, #0x6
+// CHECK-INST: and z0.s, z0.s, #0xfffffff9
+// CHECK-ENCODING: [0xa0,0xeb,0x80,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 eb 80 05 <unknown>
+
+bic z0.d, z0.d, #0x6
+// CHECK-INST: and z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-ENCODING: [0xa0,0xef,0x83,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 ef 83 05 <unknown>
+
+bic z0.d, z0.d, z0.d
+// CHECK-INST: bic z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 e0 04 <unknown>
+
+bic z23.d, z13.d, z8.d
+// CHECK-INST: bic z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0xe8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 e8 04 <unknown>
+
+bic z31.b, p7/m, z31.b, z31.b
+// CHECK-INST: bic z31.b, p7/m, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x1f,0x1b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 1b 04 <unknown>
+
+bic z31.h, p7/m, z31.h, z31.h
+// CHECK-INST: bic z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x1f,0x5b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 5b 04 <unknown>
+
+bic z31.s, p7/m, z31.s, z31.s
+// CHECK-INST: bic z31.s, p7/m, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x1f,0x9b,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 9b 04 <unknown>
+
+bic z31.d, p7/m, z31.d, z31.d
+// CHECK-INST: bic z31.d, p7/m, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x1f,0xdb,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f db 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/eon-diagnostics.s b/llvm/test/MC/AArch64/SVE/eon-diagnostics.s
new file mode 100644
index 00000000000..5b6f59ce23d
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/eon-diagnostics.s
@@ -0,0 +1,52 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate not compatible with encode/decode function.
+
+eon z5.b, z5.b, #0xfa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eon z5.b, z5.b, #0xfa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eon z5.b, z5.b, #0xfff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eon z5.b, z5.b, #0xfff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eon z5.h, z5.h, #0xfffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eon z5.h, z5.h, #0xfffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eon z5.h, z5.h, #0xfffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eon z5.h, z5.h, #0xfffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eon z5.s, z5.s, #0xfffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eon z5.s, z5.s, #0xfffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eon z5.s, z5.s, #0xffffffffffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eon z5.s, z5.s, #0xffffffffffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eon z15.d, z15.d, #0xfffffffffffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eon z15.d, z15.d, #0xfffffffffffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+eon z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: eon z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eon z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: eon z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/eon.s b/llvm/test/MC/AArch64/SVE/eon.s
new file mode 100644
index 00000000000..9f6dd265506
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/eon.s
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+eon z5.b, z5.b, #0xf9
+// CHECK-INST: eor z5.b, z5.b, #0x6
+// CHECK-ENCODING: [0x25,0x3e,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 3e 40 05 <unknown>
+
+eon z23.h, z23.h, #0xfff9
+// CHECK-INST: eor z23.h, z23.h, #0x6
+// CHECK-ENCODING: [0x37,0x7c,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 37 7c 40 05 <unknown>
+
+eon z0.s, z0.s, #0xfffffff9
+// CHECK-INST: eor z0.s, z0.s, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 40 05 <unknown>
+
+eon z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-INST: eor z0.d, z0.d, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 43 05 <unknown>
+
+eon z5.b, z5.b, #0x6
+// CHECK-INST: eor z5.b, z5.b, #0xf9
+// CHECK-ENCODING: [0xa5,0x2e,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a5 2e 40 05 <unknown>
+
+eon z23.h, z23.h, #0x6
+// CHECK-INST: eor z23.h, z23.h, #0xfff9
+// CHECK-ENCODING: [0xb7,0x6d,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 6d 40 05 <unknown>
+
+eon z0.s, z0.s, #0x6
+// CHECK-INST: eor z0.s, z0.s, #0xfffffff9
+// CHECK-ENCODING: [0xa0,0xeb,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 eb 40 05 <unknown>
+
+eon z0.d, z0.d, #0x6
+// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 ef 43 05 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/eor-diagnostics.s b/llvm/test/MC/AArch64/SVE/eor-diagnostics.s
new file mode 100644
index 00000000000..001bb9128c9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/eor-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate not compatible with encode/decode function.
+
+eor z5.b, z5.b, #0xfa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.b, z5.b, #0xfa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.b, z5.b, #0xfff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.b, z5.b, #0xfff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.h, z5.h, #0xfffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.h, z5.h, #0xfffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.h, z5.h, #0xfffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.h, z5.h, #0xfffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.s, z5.s, #0xfffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.s, z5.s, #0xfffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.s, z5.s, #0xffffffffffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.s, z5.s, #0xffffffffffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z15.d, z15.d, #0xfffffffffffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z15.d, z15.d, #0xfffffffffffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+eor z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: eor z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z0.d, p0/m, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: eor z0.d, p0/m, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+eor z21.d, z5.d, z26.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: eor z21.d, z5.d, z26.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate out of restricted predicate range
+
+eor z0.d, p8/z, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/eor.s b/llvm/test/MC/AArch64/SVE/eor.s
new file mode 100644
index 00000000000..ff058df4652
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/eor.s
@@ -0,0 +1,92 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+eor z5.b, z5.b, #0xf9
+// CHECK-INST: eor z5.b, z5.b, #0xf9
+// CHECK-ENCODING: [0xa5,0x2e,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a5 2e 40 05 <unknown>
+
+eor z23.h, z23.h, #0xfff9
+// CHECK-INST: eor z23.h, z23.h, #0xfff9
+// CHECK-ENCODING: [0xb7,0x6d,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 6d 40 05 <unknown>
+
+eor z0.s, z0.s, #0xfffffff9
+// CHECK-INST: eor z0.s, z0.s, #0xfffffff9
+// CHECK-ENCODING: [0xa0,0xeb,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 eb 40 05 <unknown>
+
+eor z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-INST: eor z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-ENCODING: [0xa0,0xef,0x43,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 ef 43 05 <unknown>
+
+eor z5.b, z5.b, #0x6
+// CHECK-INST: eor z5.b, z5.b, #0x6
+// CHECK-ENCODING: [0x25,0x3e,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 3e 40 05 <unknown>
+
+eor z23.h, z23.h, #0x6
+// CHECK-INST: eor z23.h, z23.h, #0x6
+// CHECK-ENCODING: [0x37,0x7c,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 37 7c 40 05 <unknown>
+
+eor z0.s, z0.s, #0x6
+// CHECK-INST: eor z0.s, z0.s, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x40,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 40 05 <unknown>
+
+eor z0.d, z0.d, #0x6
+// CHECK-INST: eor z0.d, z0.d, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x43,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 43 05 <unknown>
+
+eor z23.d, z13.d, z8.d
+// CHECK-INST: eor z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0xa8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 a8 04 <unknown>
+
+eor z0.d, z0.d, z0.d
+// CHECK-INST: eor z0.d, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0xa0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 a0 04 <unknown>
+
+eor z31.s, p7/m, z31.s, z31.s
+// CHECK-INST: eor z31.s, p7/m, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x1f,0x99,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 99 04 <unknown>
+
+eor z31.h, p7/m, z31.h, z31.h
+// CHECK-INST: eor z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x1f,0x59,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 59 04 <unknown>
+
+eor z31.d, p7/m, z31.d, z31.d
+// CHECK-INST: eor z31.d, p7/m, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x1f,0xd9,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f d9 04 <unknown>
+
+eor z31.b, p7/m, z31.b, z31.b
+// CHECK-INST: eor z31.b, p7/m, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x1f,0x19,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 19 04 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/mov-diagnostics.s b/llvm/test/MC/AArch64/SVE/mov-diagnostics.s
index af1ea8edae5..89f67c9f89a 100644
--- a/llvm/test/MC/AArch64/SVE/mov-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/mov-diagnostics.s
@@ -20,6 +20,24 @@ mov z0.d, xzr
// --------------------------------------------------------------------------//
+// Unpredicated mov of Z register only allowed for .d
+
+mov z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov z0.h, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov z0.h, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov z0.s, z1.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov z0.s, z1.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
// Invalid immediates
mov z0.b, #0, lsl #8 // #0, lsl #8 is not valid for .b
diff --git a/llvm/test/MC/AArch64/SVE/mov.s b/llvm/test/MC/AArch64/SVE/mov.s
index f84d0e45c1f..e3d9a7b144c 100644
--- a/llvm/test/MC/AArch64/SVE/mov.s
+++ b/llvm/test/MC/AArch64/SVE/mov.s
@@ -55,6 +55,18 @@ mov z31.b, wsp
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 3b 20 05 <unknown>
+mov z0.d, z0.d
+// CHECK-INST: mov z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+mov z31.d, z0.d
+// CHECK-INST: mov z31.d, z0.d
+// CHECK-ENCODING: [0x1f,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 1f 30 60 04 <unknown>
+
mov z5.b, #-128
// CHECK-INST: mov z5.b, #-128
// CHECK-ENCODING: [0x05,0xd0,0x38,0x25]
diff --git a/llvm/test/MC/AArch64/SVE/orn-diagnostics.s b/llvm/test/MC/AArch64/SVE/orn-diagnostics.s
new file mode 100644
index 00000000000..ff9827e6787
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orn-diagnostics.s
@@ -0,0 +1,52 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate not compatible with encode/decode function.
+
+orn z5.b, z5.b, #0xfa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orn z5.b, z5.b, #0xfa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn z5.b, z5.b, #0xfff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orn z5.b, z5.b, #0xfff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn z5.h, z5.h, #0xfffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orn z5.h, z5.h, #0xfffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn z5.h, z5.h, #0xfffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orn z5.h, z5.h, #0xfffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn z5.s, z5.s, #0xfffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orn z5.s, z5.s, #0xfffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn z5.s, z5.s, #0xffffffffffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orn z5.s, z5.s, #0xffffffffffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn z15.d, z15.d, #0xfffffffffffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orn z15.d, z15.d, #0xfffffffffffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+orn z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: orn z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orn z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: orn z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/orn.s b/llvm/test/MC/AArch64/SVE/orn.s
new file mode 100644
index 00000000000..2a336ed4bfc
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orn.s
@@ -0,0 +1,56 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+orn z5.b, z5.b, #0xf9
+// CHECK-INST: orr z5.b, z5.b, #0x6
+// CHECK-ENCODING: [0x25,0x3e,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 3e 00 05 <unknown>
+
+orn z23.h, z23.h, #0xfff9
+// CHECK-INST: orr z23.h, z23.h, #0x6
+// CHECK-ENCODING: [0x37,0x7c,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 37 7c 00 05 <unknown>
+
+orn z0.s, z0.s, #0xfffffff9
+// CHECK-INST: orr z0.s, z0.s, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 00 05 <unknown>
+
+orn z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-INST: orr z0.d, z0.d, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 03 05 <unknown>
+
+orn z5.b, z5.b, #0x6
+// CHECK-INST: orr z5.b, z5.b, #0xf9
+// CHECK-ENCODING: [0xa5,0x2e,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a5 2e 00 05 <unknown>
+
+orn z23.h, z23.h, #0x6
+// CHECK-INST: orr z23.h, z23.h, #0xfff9
+// CHECK-ENCODING: [0xb7,0x6d,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 6d 00 05 <unknown>
+
+orn z0.s, z0.s, #0x6
+// CHECK-INST: orr z0.s, z0.s, #0xfffffff9
+// CHECK-ENCODING: [0xa0,0xeb,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 eb 00 05 <unknown>
+
+orn z0.d, z0.d, #0x6
+// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 ef 03 05 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/orr-diagnostics.s b/llvm/test/MC/AArch64/SVE/orr-diagnostics.s
new file mode 100644
index 00000000000..b244d3f09f1
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orr-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate not compatible with encode/decode function.
+
+orr z5.b, z5.b, #0xfa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orr z5.b, z5.b, #0xfa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr z5.b, z5.b, #0xfff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orr z5.b, z5.b, #0xfff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr z5.h, z5.h, #0xfffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orr z5.h, z5.h, #0xfffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr z5.h, z5.h, #0xfffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orr z5.h, z5.h, #0xfffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr z5.s, z5.s, #0xfffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orr z5.s, z5.s, #0xfffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr z5.s, z5.s, #0xffffffffffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orr z5.s, z5.s, #0xffffffffffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr z15.d, z15.d, #0xfffffffffffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: orr z15.d, z15.d, #0xfffffffffffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+orr z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: orr z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+orr z0.d, p0/m, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: orr z0.d, p0/m, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+orr z21.d, z5.d, z26.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: orr z21.d, z5.d, z26.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate out of restricted predicate range
+
+orr z0.d, p8/z, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: orr z0.d, p8/z, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/orr.s b/llvm/test/MC/AArch64/SVE/orr.s
new file mode 100644
index 00000000000..f1c8bf761fc
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/orr.s
@@ -0,0 +1,94 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+
+orr z5.b, z5.b, #0xf9
+// CHECK-INST: orr z5.b, z5.b, #0xf9
+// CHECK-ENCODING: [0xa5,0x2e,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a5 2e 00 05 <unknown>
+
+orr z23.h, z23.h, #0xfff9
+// CHECK-INST: orr z23.h, z23.h, #0xfff9
+// CHECK-ENCODING: [0xb7,0x6d,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 6d 00 05 <unknown>
+
+orr z0.s, z0.s, #0xfffffff9
+// CHECK-INST: orr z0.s, z0.s, #0xfffffff9
+// CHECK-ENCODING: [0xa0,0xeb,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 eb 00 05 <unknown>
+
+orr z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-INST: orr z0.d, z0.d, #0xfffffffffffffff9
+// CHECK-ENCODING: [0xa0,0xef,0x03,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: a0 ef 03 05 <unknown>
+
+orr z5.b, z5.b, #0x6
+// CHECK-INST: orr z5.b, z5.b, #0x6
+// CHECK-ENCODING: [0x25,0x3e,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 25 3e 00 05 <unknown>
+
+orr z23.h, z23.h, #0x6
+// CHECK-INST: orr z23.h, z23.h, #0x6
+// CHECK-ENCODING: [0x37,0x7c,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 37 7c 00 05 <unknown>
+
+orr z0.s, z0.s, #0x6
+// CHECK-INST: orr z0.s, z0.s, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x00,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 00 05 <unknown>
+
+orr z0.d, z0.d, #0x6
+// CHECK-INST: orr z0.d, z0.d, #0x6
+// CHECK-ENCODING: [0x20,0xf8,0x03,0x05]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 f8 03 05 <unknown>
+
+orr z0.d, z0.d, z0.d // should use mov-alias
+// CHECK-INST: mov z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x30,0x60,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 30 60 04 <unknown>
+
+orr z23.d, z13.d, z8.d // should not use mov-alias
+// CHECK-INST: orr z23.d, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0x31,0x68,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: b7 31 68 04 <unknown>
+
+orr z31.b, p7/m, z31.b, z31.b
+// CHECK-INST: orr z31.b, p7/m, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0x1f,0x18,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 18 04 <unknown>
+
+orr z31.h, p7/m, z31.h, z31.h
+// CHECK-INST: orr z31.h, p7/m, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0x1f,0x58,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 58 04 <unknown>
+
+orr z31.s, p7/m, z31.s, z31.s
+// CHECK-INST: orr z31.s, p7/m, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0x1f,0x98,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f 98 04 <unknown>
+
+orr z31.d, p7/m, z31.d, z31.d
+// CHECK-INST: orr z31.d, p7/m, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0x1f,0xd8,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 1f d8 04 <unknown>
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