1 files changed, 67 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/SVE/eor-diagnostics.s b/llvm/test/MC/AArch64/SVE/eor-diagnostics.s
new file mode 100644
index 00000000000..001bb9128c9
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/eor-diagnostics.s
@@ -0,0 +1,67 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Immediate not compatible with encode/decode function.
+
+eor z5.b, z5.b, #0xfa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.b, z5.b, #0xfa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.b, z5.b, #0xfff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.b, z5.b, #0xfff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.h, z5.h, #0xfffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.h, z5.h, #0xfffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.h, z5.h, #0xfffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.h, z5.h, #0xfffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.s, z5.s, #0xfffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.s, z5.s, #0xfffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z5.s, z5.s, #0xffffffffffffff9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z5.s, z5.s, #0xffffffffffffff9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z15.d, z15.d, #0xfffffffffffffffa
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
+// CHECK-NEXT: eor z15.d, z15.d, #0xfffffffffffffffa
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+eor z7.d, z8.d, #254
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: eor z7.d, z8.d, #254
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+eor z0.d, p0/m, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: eor z0.d, p0/m, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element size specifiers should match.
+eor z21.d, z5.d, z26.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: eor z21.d, z5.d, z26.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Predicate out of restricted predicate range
+
+eor z0.d, p8/z, z0.d, z1.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: eor z0.d, p8/z, z0.d, z1.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: