diff options
Diffstat (limited to 'llvm/test/MC/AArch64/SVE/orn-diagnostics.s')
| -rw-r--r-- | llvm/test/MC/AArch64/SVE/orn-diagnostics.s | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/SVE/orn-diagnostics.s b/llvm/test/MC/AArch64/SVE/orn-diagnostics.s new file mode 100644 index 00000000000..ff9827e6787 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE/orn-diagnostics.s @@ -0,0 +1,52 @@ +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s + +// --------------------------------------------------------------------------// +// Immediate not compatible with encode/decode function. + +orn z5.b, z5.b, #0xfa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.b, z5.b, #0xfa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.b, z5.b, #0xfff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.b, z5.b, #0xfff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.h, z5.h, #0xfffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.h, z5.h, #0xfffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.h, z5.h, #0xfffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.h, z5.h, #0xfffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.s, z5.s, #0xfffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.s, z5.s, #0xfffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z5.s, z5.s, #0xffffffffffffff9 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z5.s, z5.s, #0xffffffffffffff9 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z15.d, z15.d, #0xfffffffffffffffa +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate +// CHECK-NEXT: orn z15.d, z15.d, #0xfffffffffffffffa +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +// --------------------------------------------------------------------------// +// Source and Destination Registers must match + +orn z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: orn z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: + +orn z7.d, z8.d, #254 +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register +// CHECK-NEXT: orn z7.d, z8.d, #254 +// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
