diff options
Diffstat (limited to 'llvm/test/CodeGen')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/branch-relaxation.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/indirectbr.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/option-rvc.ll | 2 |
3 files changed, 4 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation.ll b/llvm/test/CodeGen/RISCV/branch-relaxation.ll index cd589dd9cab..56f0f27a064 100644 --- a/llvm/test/CodeGen/RISCV/branch-relaxation.ll +++ b/llvm/test/CodeGen/RISCV/branch-relaxation.ll @@ -25,6 +25,7 @@ tail: ret void } +; TODO: Extend simm12's MCOperandPredicate so the jalr zero is printed as a jr. define i32 @relax_jal(i1 %a) nounwind { ; CHECK-LABEL: relax_jal: ; CHECK: # %bb.0: @@ -32,7 +33,7 @@ define i32 @relax_jal(i1 %a) nounwind { ; CHECK-NEXT: bnez a0, .LBB1_1 ; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: lui a0, %hi(.LBB1_2) -; CHECK-NEXT: jalr zero, a0, %lo(.LBB1_2) +; CHECK-NEXT: jalr zero, %lo(.LBB1_2)(a0) ; CHECK-NEXT: .LBB1_1: # %iftrue ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP diff --git a/llvm/test/CodeGen/RISCV/indirectbr.ll b/llvm/test/CodeGen/RISCV/indirectbr.ll index 1d916b8e108..e734de3c8e4 100644 --- a/llvm/test/CodeGen/RISCV/indirectbr.ll +++ b/llvm/test/CodeGen/RISCV/indirectbr.ll @@ -25,7 +25,7 @@ define i32 @indirectbr_with_offset(i8* %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: jalr zero, a0, 1380 +; RV32I-NEXT: jr 1380(a0) ; RV32I-NEXT: .LBB1_1: ; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: lw ra, 12(sp) diff --git a/llvm/test/CodeGen/RISCV/option-rvc.ll b/llvm/test/CodeGen/RISCV/option-rvc.ll index 3c207bd424f..a0f09c052a4 100644 --- a/llvm/test/CodeGen/RISCV/option-rvc.ll +++ b/llvm/test/CodeGen/RISCV/option-rvc.ll @@ -8,7 +8,7 @@ define i32 @add(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: add: ; CHECK: add a0, a1, a0 -; CHECK-NEXT: jalr zero, ra, 0 +; CHECK-NEXT: jalr zero, 0(ra) tail call void asm sideeffect ".option rvc", ""() %add = add nsw i32 %b, %a ret i32 %add |
