diff options
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 25 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/branch-relaxation.ll | 3 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/indirectbr.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/RISCV/option-rvc.ll | 2 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/compress-rv32i.s | 4 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/fixups.s | 6 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv32e-valid.s | 2 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rv32i-valid.s | 24 | ||||
| -rw-r--r-- | llvm/test/MC/RISCV/rvi-aliases-valid.s | 28 |
9 files changed, 60 insertions, 36 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index b017307b461..69bde15f121 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -357,7 +357,7 @@ def JAL : RVInstJ<OPC_JAL, (outs GPR:$rd), (ins simm21_lsb0_jal:$imm20), let isCall = 1 in def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12), - "jalr", "$rd, $rs1, $imm12">; + "jalr", "$rd, ${imm12}(${rs1})">; } // hasSideEffects = 0, mayLoad = 0, mayStore = 0 def BEQ : BranchCC_rri<0b000, "beq">; @@ -597,12 +597,23 @@ def : InstAlias<"bgtu $rs, $rt, $offset", def : InstAlias<"bleu $rs, $rt, $offset", (BGEU GPR:$rt, GPR:$rs, simm13_lsb0:$offset), 0>; -// "ret" has more weight since "ret" and "jr" alias the same "jalr" instruction. -def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>; -def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>; -def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0)>; -def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0)>; -def : InstAlias<"ret", (JALR X0, X1, 0), 2>; +def : InstAlias<"j $offset", (JAL X0, simm21_lsb0_jal:$offset)>; +def : InstAlias<"jal $offset", (JAL X1, simm21_lsb0_jal:$offset)>; + +// Non-zero offset aliases of "jalr" are the lowest weight, followed by the +// two-register form, then the one-register forms and finally "ret". +def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>; +def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>; +def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>; +def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>; +def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>; +def : InstAlias<"ret", (JALR X0, X1, 0), 4>; + +// Non-canonical forms for jump targets also accepted by the assembler. +def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12:$offset), 0>; +def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>; +def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>; + // TODO call // TODO tail diff --git a/llvm/test/CodeGen/RISCV/branch-relaxation.ll b/llvm/test/CodeGen/RISCV/branch-relaxation.ll index cd589dd9cab..56f0f27a064 100644 --- a/llvm/test/CodeGen/RISCV/branch-relaxation.ll +++ b/llvm/test/CodeGen/RISCV/branch-relaxation.ll @@ -25,6 +25,7 @@ tail: ret void } +; TODO: Extend simm12's MCOperandPredicate so the jalr zero is printed as a jr. define i32 @relax_jal(i1 %a) nounwind { ; CHECK-LABEL: relax_jal: ; CHECK: # %bb.0: @@ -32,7 +33,7 @@ define i32 @relax_jal(i1 %a) nounwind { ; CHECK-NEXT: bnez a0, .LBB1_1 ; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: lui a0, %hi(.LBB1_2) -; CHECK-NEXT: jalr zero, a0, %lo(.LBB1_2) +; CHECK-NEXT: jalr zero, %lo(.LBB1_2)(a0) ; CHECK-NEXT: .LBB1_1: # %iftrue ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP diff --git a/llvm/test/CodeGen/RISCV/indirectbr.ll b/llvm/test/CodeGen/RISCV/indirectbr.ll index 1d916b8e108..e734de3c8e4 100644 --- a/llvm/test/CodeGen/RISCV/indirectbr.ll +++ b/llvm/test/CodeGen/RISCV/indirectbr.ll @@ -25,7 +25,7 @@ define i32 @indirectbr_with_offset(i8* %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: jalr zero, a0, 1380 +; RV32I-NEXT: jr 1380(a0) ; RV32I-NEXT: .LBB1_1: ; RV32I-NEXT: mv a0, zero ; RV32I-NEXT: lw ra, 12(sp) diff --git a/llvm/test/CodeGen/RISCV/option-rvc.ll b/llvm/test/CodeGen/RISCV/option-rvc.ll index 3c207bd424f..a0f09c052a4 100644 --- a/llvm/test/CodeGen/RISCV/option-rvc.ll +++ b/llvm/test/CodeGen/RISCV/option-rvc.ll @@ -8,7 +8,7 @@ define i32 @add(i32 %a, i32 %b) nounwind { ; CHECK-LABEL: add: ; CHECK: add a0, a1, a0 -; CHECK-NEXT: jalr zero, ra, 0 +; CHECK-NEXT: jalr zero, 0(ra) tail call void asm sideeffect ".option rvc", ""() %add = add nsw i32 %b, %a ret i32 %add diff --git a/llvm/test/MC/RISCV/compress-rv32i.s b/llvm/test/MC/RISCV/compress-rv32i.s index 149279c4330..1f8835faf35 100644 --- a/llvm/test/MC/RISCV/compress-rv32i.s +++ b/llvm/test/MC/RISCV/compress-rv32i.s @@ -168,7 +168,7 @@ lw ra, 252(sp) # CHECK-ALIAS: ret # CHECK-INST: c.jr ra # CHECK: # encoding: [0x82,0x80] -jalr zero, ra, 0 +jalr zero, 0(ra) # CHECK-BYTES: 92 80 # CHECK-ALIAS: add ra, zero, tp @@ -192,7 +192,7 @@ ebreak # CHECK-ALIAS: jalr s0 # CHECK-INST: c.jalr s0 # CHECK: # encoding: [0x02,0x94] -jalr ra, s0, 0 +jalr ra, 0(s0) # CHECK-BYTES: 3e 94 # CHECK-ALIAS: add s0, s0, a5 diff --git a/llvm/test/MC/RISCV/fixups.s b/llvm/test/MC/RISCV/fixups.s index f0377debabb..ca0ee131fb8 100644 --- a/llvm/test/MC/RISCV/fixups.s +++ b/llvm/test/MC/RISCV/fixups.s @@ -68,16 +68,16 @@ func: call func # CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call # CHECK-INSTR: auipc ra, 0 -# CHECK-INSTR: jalr ra, ra, -100 +# CHECK-INSTR: jalr ra, -100(ra) .fill 10000 call func # CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call # CHECK-INSTR: auipc ra, 1048574 -# CHECK-INSTR: jalr ra, ra, -1916 +# CHECK-INSTR: jalr ra, -1916(ra) .fill 20888 call func # CHECK-FIXUP: fixup A - offset: 0, value: func, kind: fixup_riscv_call # CHECK-INSTR: auipc ra, 1048568 -# CHECK-INSTR: jalr ra, ra, 1764 +# CHECK-INSTR: jalr ra, 1764(ra) diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s index 25419768ad9..42b85fb0535 100644 --- a/llvm/test/MC/RISCV/rv32e-valid.s +++ b/llvm/test/MC/RISCV/rv32e-valid.s @@ -14,7 +14,7 @@ auipc x1, 2 # CHECK-ASM-AND-OBJ: jal sp, 4 jal x2, 4 -# CHECK-ASM-AND-OBJ: jalr gp, gp, 4 +# CHECK-ASM-AND-OBJ: jalr gp, 4(gp) jalr x3, x3, 4 # CHECK-ASM-AND-OBJ: beq tp, t0, 8 diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s index 3611d71ac43..23ed9a2b4e8 100644 --- a/llvm/test/MC/RISCV/rv32i-valid.s +++ b/llvm/test/MC/RISCV/rv32i-valid.s @@ -94,27 +94,21 @@ jal s0, (0xff-99) # CHECK-OBJ: jal zero, 0 jal zero, . -# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048 +# CHECK-ASM-AND-OBJ: jalr a0, -2048(a1) # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80] -jalr a0, a1, -2048 -# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048 +jalr a0, -2048(a1) +# CHECK-ASM-AND-OBJ: jalr a0, -2048(a1) # CHECK-ASM: encoding: [0x67,0x85,0x05,0x80] -jalr a0, a1, ~2047 -# CHECK-ASM-AND-OBJ: jalr a0, a1, 0 -# CHECK-ASM: encoding: [0x67,0x85,0x05,0x00] -jalr a0, a1, !1 -# CHECK-ASM-AND-OBJ: jalr a0, a1, -2048 -# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80] -jalr a0, a1, %lo(2048) -# CHECK-ASM-AND-OBJ: jalr t2, t1, 2047 +jalr a0, %lo(2048)(a1) +# CHECK-ASM-AND-OBJ: jalr t2, 2047(t1) # CHECK-ASM: encoding: [0xe7,0x03,0xf3,0x7f] -jalr t2, t1, 2047 -# CHECK-ASM-AND-OBJ: jalr sp, zero, 256 +jalr t2, 2047(t1) +# CHECK-ASM-AND-OBJ: jalr sp, 256(zero) # CHECK-ASM: encoding: [0x67,0x01,0x00,0x10] jalr sp, zero, 256 -# CHECK-ASM-AND-OBJ: jalr a1, a2, 30 +# CHECK-ASM-AND-OBJ: jalr a1, 30(a2) # CHECK-ASM: encoding: [0xe7,0x05,0xe6,0x01] -jalr a1, a2, CONST +jalr a1, CONST(a2) # CHECK-ASM-AND-OBJ: beq s1, s1, 102 # CHECK-ASM: encoding: [0x63,0x83,0x94,0x06] diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s index a3050aa46f6..71a50ec95aa 100644 --- a/llvm/test/MC/RISCV/rvi-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -139,13 +139,31 @@ jal foo # CHECK-OBJ: jal 0 # CHECK-OBJ: R_RISCV_JAL a0 jal a0 -# CHECK-S-OBJ-NOALIAS: jalr zero, s4, 0 +# CHECK-S-OBJ-NOALIAS: jalr zero, 0(s4) # CHECK-S-OBJ: jr s4 jr x20 -# CHECK-S-OBJ-NOALIAS: jalr ra, s5, 0 -# CHECK-S-OBJ: jalr s5 -jalr x21 -# CHECK-S-OBJ-NOALIAS: jalr zero, ra, 0 +# CHECK-S-OBJ-NOALIAS: jalr zero, 6(s5) +# CHECK-S-OBJ: jr 6(s5) +jr 6(x21) +# CHECK-S-OBJ-NOALIAS: jalr zero, 7(s6) +# CHECK-S-OBJ: jr 7(s6) +jr x22, 7 +# CHECK-S-OBJ-NOALIAS: jalr ra, 0(s4) +# CHECK-S-OBJ: jalr s4 +jalr x20 +# CHECK-S-OBJ-NOALIAS: jalr ra, 8(s5) +# CHECK-S-OBJ: jalr 8(s5) +jalr 8(x21) +# CHECK-S-OBJ-NOALIAS: jalr s6, 0(s7) +# CHECK-S-OBJ: jalr s6, s7 +jalr x22, x23 +# CHECK-S-OBJ-NOALIAS: jalr ra, 9(s8) +# CHECK-S-OBJ: jalr 9(s8) +jalr x24, 9 +# CHECK-S-OBJ-NOALIAS: jalr s9, 11(s10) +# CHECK-S-OBJ: jalr s9, 11(s10) +jalr x25, x26, 11 +# CHECK-S-OBJ-NOALIAS: jalr zero, 0(ra) # CHECK-S-OBJ: ret ret # TODO call |
