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-rw-r--r--llvm/test/CodeGen/RISCV/option-rvc.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/RISCV/option-rvc.ll b/llvm/test/CodeGen/RISCV/option-rvc.ll
index 3c207bd424f..a0f09c052a4 100644
--- a/llvm/test/CodeGen/RISCV/option-rvc.ll
+++ b/llvm/test/CodeGen/RISCV/option-rvc.ll
@@ -8,7 +8,7 @@
define i32 @add(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: add:
; CHECK: add a0, a1, a0
-; CHECK-NEXT: jalr zero, ra, 0
+; CHECK-NEXT: jalr zero, 0(ra)
tail call void asm sideeffect ".option rvc", ""()
%add = add nsw i32 %b, %a
ret i32 %add
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