diff options
Diffstat (limited to 'llvm/test/CodeGen/X86')
161 files changed, 776 insertions, 776 deletions
diff --git a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir index b4afd808ac1..31f1da5c674 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/avoid-matchtable-crash.mir @@ -9,7 +9,7 @@ ... --- name: test_check_type -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir index e0e1c2d3ca8..28ed57dcdf8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v128.mir @@ -24,7 +24,7 @@ ... --- name: test_add_v16i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -50,7 +50,7 @@ body: | ... --- name: test_add_v8i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -76,7 +76,7 @@ body: | ... --- name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -102,7 +102,7 @@ body: | ... --- name: test_add_v2i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir index 59b0b14d585..98b38514b7e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v256.mir @@ -27,7 +27,7 @@ ... --- name: test_add_v32i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -72,7 +72,7 @@ body: | ... --- name: test_add_v16i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -117,7 +117,7 @@ body: | ... --- name: test_add_v8i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -162,7 +162,7 @@ body: | ... --- name: test_add_v4i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir index 4120ed5ce6f..2aece951268 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add-v512.mir @@ -31,7 +31,7 @@ ... --- name: test_add_v64i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -78,7 +78,7 @@ body: | ... --- name: test_add_v32i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -125,7 +125,7 @@ body: | ... --- name: test_add_v16i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -168,7 +168,7 @@ body: | ... --- name: test_add_v8i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -211,7 +211,7 @@ body: | ... --- name: test_add_v64i8_2 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir index f3f5d4cdac7..69c7dd4cb72 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir @@ -15,7 +15,7 @@ --- name: test_add_i1 # CHECK-LABEL: name: test_add_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_add_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_add_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir index abde7a28c14..1f09e4639df 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir @@ -30,7 +30,7 @@ ... --- name: test_and_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -57,7 +57,7 @@ body: | ... --- name: test_and_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -82,7 +82,7 @@ body: | ... --- name: test_and_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -107,7 +107,7 @@ body: | ... --- name: test_and_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -132,7 +132,7 @@ body: | ... --- name: test_and_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir index eece3021c5e..0964e06d2b7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir @@ -7,7 +7,7 @@ ... --- name: test_ashr -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: test_ashr_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir index 2cf3eba8ceb..4e11683a07c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-brcond.mir @@ -18,7 +18,7 @@ --- name: test # ALL-LABEL: name: test -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir index 055ff77f1da..442fb2ffbbb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir @@ -35,7 +35,7 @@ ... --- name: test_cmp_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -64,7 +64,7 @@ body: | ... --- name: test_cmp_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -93,7 +93,7 @@ body: | ... --- name: test_cmp_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -122,7 +122,7 @@ body: | ... --- name: test_cmp_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -151,7 +151,7 @@ body: | ... --- name: test_cmp_p0 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir index aafedd3b5b7..c891608d60a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir @@ -64,7 +64,7 @@ ... --- name: test_sext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -94,7 +94,7 @@ body: | ... --- name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -117,7 +117,7 @@ body: | ... --- name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -140,7 +140,7 @@ body: | ... --- name: test_sext_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -163,7 +163,7 @@ body: | ... --- name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -190,7 +190,7 @@ body: | ... --- name: test_zext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -213,7 +213,7 @@ body: | ... --- name: test_zext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -236,7 +236,7 @@ body: | ... --- name: test_zext_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -259,7 +259,7 @@ body: | ... --- name: test_anyext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -284,7 +284,7 @@ body: | ... --- name: test_anyext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -307,7 +307,7 @@ body: | ... --- name: test_anyext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -330,7 +330,7 @@ body: | ... --- name: test_anyext_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir index 71f1facfb81..aafba4119bb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir @@ -92,7 +92,7 @@ ... --- name: test_zext_i1toi8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -126,7 +126,7 @@ body: | ... --- name: test_zext_i1toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -159,7 +159,7 @@ body: | ... --- name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -193,7 +193,7 @@ body: | ... --- name: test_zext_i8toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -221,7 +221,7 @@ body: | ... --- name: test_zext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -249,7 +249,7 @@ body: | ... --- name: test_zext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -277,7 +277,7 @@ body: | ... --- name: test_sext_i1toi8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -303,7 +303,7 @@ body: | ... --- name: test_sext_i1toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -329,7 +329,7 @@ body: | ... --- name: test_sext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -356,7 +356,7 @@ body: | ... --- name: test_sext_i8toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -384,7 +384,7 @@ body: | ... --- name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -412,7 +412,7 @@ body: | ... --- name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -440,7 +440,7 @@ body: | ... --- name: test_anyext_i1toi8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -470,7 +470,7 @@ body: | ... --- name: test_anyext_i1toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -500,7 +500,7 @@ body: | ... --- name: test_anyext_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -530,7 +530,7 @@ body: | ... --- name: test_anyext_i8toi16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -558,7 +558,7 @@ body: | ... --- name: test_anyext_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -586,7 +586,7 @@ body: | ... --- name: test_anyext_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir index 05e2638bfea..8142fe25d6c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fadd-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fadd_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fadd_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir index cb0c685ce3e..23f3bf4796a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fdiv-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fdiv_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fdiv_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir index 347d56a9094..0a888ab6744 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fmul-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fmul_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fmul_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir index 58786f3e53f..6c47a859876 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fpext-scalar.mir @@ -11,7 +11,7 @@ ... --- name: test -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir index fbe139f9d70..057ab7c4c17 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fptrunc-scalar.mir @@ -10,7 +10,7 @@ ... --- name: test_fptrunc -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir index 7979d92e51f..897fcf2c62a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fsub-scalar.mir @@ -15,7 +15,7 @@ ... --- name: test_fsub_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -54,7 +54,7 @@ body: | ... --- name: test_fsub_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir index 5486b39ab47..49fbe4bc362 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec256.mir @@ -8,7 +8,7 @@ --- name: test_insert_128 # ALL-LABEL: name: test_insert_128 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir index d6cb9d42db0..99ac3d4ab7b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-insert-vec512.mir @@ -12,7 +12,7 @@ ... --- name: test_insert_128 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -38,7 +38,7 @@ body: | ... --- name: test_insert_256 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir index 8cca8361bee..fd284ebfc61 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir @@ -7,7 +7,7 @@ ... --- name: test_lshr -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: test_lshr_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir index ad1c713a87c..8e2bc5d4f28 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-32.mir @@ -3,7 +3,7 @@ --- name: test_memop_s8tos32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false body: | @@ -38,7 +38,7 @@ body: | ... --- name: test_memop_s64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false liveins: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir index c7de33ddb58..a550a823831 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-memop-scalar-64.mir @@ -3,7 +3,7 @@ --- name: test_memop_s8tos32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false body: | @@ -38,7 +38,7 @@ body: | ... --- name: test_memop_s64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false liveins: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir index 122c45212a8..d4c753435b4 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir @@ -22,7 +22,7 @@ ... --- name: test_mul_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -52,7 +52,7 @@ body: | ... --- name: test_mul_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -78,7 +78,7 @@ body: | ... --- name: test_mul_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -104,7 +104,7 @@ body: | ... --- name: test_mul_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir index 659e3aec71f..3b8455684f3 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir @@ -22,7 +22,7 @@ --- name: test_mul_v8i16 # ALL-LABEL: name: test_mul_v8i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -52,7 +52,7 @@ body: | --- name: test_mul_v4i32 # ALL-LABEL: name: test_mul_v4i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -82,7 +82,7 @@ body: | --- name: test_mul_v2i64 # ALL-LABEL: name: test_mul_v2i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir index 175bcbca52c..4965b069715 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir @@ -22,7 +22,7 @@ --- name: test_mul_v16i16 # ALL-LABEL: name: test_mul_v16i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -52,7 +52,7 @@ body: | --- name: test_mul_v8i32 # ALL-LABEL: name: test_mul_v8i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -82,7 +82,7 @@ body: | --- name: test_mul_v4i64 # ALL-LABEL: name: test_mul_v4i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir index e7dbcb2d76c..77a94581b66 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir @@ -24,7 +24,7 @@ --- name: test_mul_v32i16 # ALL-LABEL: name: test_mul_v32i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -54,7 +54,7 @@ body: | --- name: test_mul_v16i32 # ALL-LABEL: name: test_mul_v16i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: @@ -84,7 +84,7 @@ body: | --- name: test_mul_v8i64 # ALL-LABEL: name: test_mul_v8i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir index 6da13f654f1..ee571d3430c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir @@ -30,7 +30,7 @@ ... --- name: test_or_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -60,7 +60,7 @@ body: | ... --- name: test_or_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_or_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -110,7 +110,7 @@ body: | ... --- name: test_or_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -135,7 +135,7 @@ body: | ... --- name: test_or_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir index 25ffa8c3f45..cb8c790e6c5 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir @@ -118,7 +118,7 @@ ... --- name: test_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -186,7 +186,7 @@ body: | ... --- name: test_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -250,7 +250,7 @@ body: | ... --- name: test_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -314,7 +314,7 @@ body: | ... --- name: test_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -382,7 +382,7 @@ body: | ... --- name: test_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -450,7 +450,7 @@ body: | ... --- name: test_float -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -517,7 +517,7 @@ body: | ... --- name: test_double -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir index ee4be22f95e..16ffb9510ae 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir @@ -7,7 +7,7 @@ ... --- name: test_shl -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true @@ -54,7 +54,7 @@ body: | ... --- name: test_shl_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir index c5775f3901c..f6be978db09 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v128.mir @@ -24,7 +24,7 @@ ... --- name: test_sub_v16i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -49,7 +49,7 @@ body: | ... --- name: test_sub_v8i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -74,7 +74,7 @@ body: | ... --- name: test_sub_v4i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -99,7 +99,7 @@ body: | ... --- name: test_sub_v2i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir index 49a7ce5a01f..6f47c5fa08d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v256.mir @@ -25,7 +25,7 @@ ... --- name: test_sub_v32i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -50,7 +50,7 @@ body: | ... --- name: test_sub_v16i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -75,7 +75,7 @@ body: | ... --- name: test_sub_v8i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -100,7 +100,7 @@ body: | ... --- name: test_sub_v4i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir index 725299a8920..400b46e77ee 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub-v512.mir @@ -25,7 +25,7 @@ ... --- name: test_sub_v64i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -50,7 +50,7 @@ body: | ... --- name: test_sub_v32i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -75,7 +75,7 @@ body: | ... --- name: test_sub_v16i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -100,7 +100,7 @@ body: | ... --- name: test_sub_v8i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir index ff4af534baa..74289897b6a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir @@ -13,7 +13,7 @@ ... --- name: test_sub_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -43,7 +43,7 @@ body: | ... --- name: test_sub_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir index 13ac1e072b4..754402492b8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir @@ -30,7 +30,7 @@ ... --- name: test_xor_i1 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_xor_i8 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -80,7 +80,7 @@ body: | ... --- name: test_xor_i16 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -105,7 +105,7 @@ body: | ... --- name: test_xor_i32 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: @@ -130,7 +130,7 @@ body: | ... --- name: test_xor_i64 -alignment: 4 +alignment: 16 legalized: false regBankSelected: false registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir index 98a6693645a..7ce86c93a95 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir @@ -26,7 +26,7 @@ --- name: test_mul_vec256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -49,7 +49,7 @@ body: | ... --- name: test_add_vec256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -72,7 +72,7 @@ body: | ... --- name: test_sub_vec256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -96,7 +96,7 @@ body: | --- name: test_load_v8i32_noalign # CHECK-LABEL: name: test_load_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -118,7 +118,7 @@ body: | --- name: test_store_v8i32_noalign # CHECK-LABEL: name: test_store_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir index c7c64cfe96a..7da4b0122e6 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir @@ -29,7 +29,7 @@ --- name: test_mul_vec512 # CHECK-LABEL: name: test_mul_vec512 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -49,7 +49,7 @@ body: | --- name: test_add_vec512 # CHECK-LABEL: name: test_add_vec512 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -69,7 +69,7 @@ body: | --- name: test_sub_vec512 # CHECK-LABEL: name: test_sub_vec512 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -89,7 +89,7 @@ body: | name: test_load_v16i32_noalign # CHECK-LABEL: name: test_load_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: @@ -111,7 +111,7 @@ body: | --- name: test_store_v16i32_noalign # CHECK-LABEL: name: test_store_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir index c06c2609528..cd5fa912add 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir @@ -10,7 +10,7 @@ --- name: test_uadde_i32 # CHECK-LABEL: name: test_uadde_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false # CHECK: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir index 2b730581d86..9cf6845b3a0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir @@ -463,7 +463,7 @@ ... --- name: test_add_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -499,7 +499,7 @@ body: | ... --- name: test_add_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -535,7 +535,7 @@ body: | ... --- name: test_add_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -571,7 +571,7 @@ body: | ... --- name: test_add_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -607,7 +607,7 @@ body: | ... --- name: test_mul_gpr -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -656,7 +656,7 @@ body: | ... --- name: test_add_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -704,7 +704,7 @@ body: | ... --- name: test_add_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -752,7 +752,7 @@ body: | ... --- name: test_fsub_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -795,7 +795,7 @@ body: | ... --- name: test_fmul_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -838,7 +838,7 @@ body: | ... --- name: test_fdiv_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -881,7 +881,7 @@ body: | ... --- name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -917,7 +917,7 @@ body: | ... --- name: test_add_v4f32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -953,7 +953,7 @@ body: | ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -982,7 +982,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1011,7 +1011,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1040,7 +1040,7 @@ body: | ... --- name: test_load_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: false @@ -1070,7 +1070,7 @@ body: | ... --- name: test_load_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1104,7 +1104,7 @@ body: | ... --- name: test_load_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1138,7 +1138,7 @@ body: | ... --- name: test_load_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1167,7 +1167,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1199,7 +1199,7 @@ body: | ... --- name: test_store_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1231,7 +1231,7 @@ body: | ... --- name: test_store_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1270,7 +1270,7 @@ body: | ... --- name: test_store_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: false selected: false @@ -1309,7 +1309,7 @@ body: | ... --- name: constInt_check -alignment: 4 +alignment: 16 legalized: true registers: - { id: 0, class: _ } @@ -1339,7 +1339,7 @@ body: | ... --- name: trunc_check -alignment: 4 +alignment: 16 legalized: true registers: - { id: 0, class: _ } @@ -1402,7 +1402,7 @@ body: | ... --- name: test_icmp_eq_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1443,7 +1443,7 @@ body: | ... --- name: test_icmp_eq_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1484,7 +1484,7 @@ body: | ... --- name: test_icmp_eq_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1519,7 +1519,7 @@ body: | ... --- name: test_icmp_eq_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1554,7 +1554,7 @@ body: | ... --- name: test_xor_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1584,7 +1584,7 @@ body: | ... --- name: test_or_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1614,7 +1614,7 @@ body: | ... --- name: test_and_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1644,7 +1644,7 @@ body: | ... --- name: test_and_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1674,7 +1674,7 @@ body: | ... --- name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1696,7 +1696,7 @@ body: | ... --- name: test_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1722,7 +1722,7 @@ body: | ... --- name: test_undef2 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1758,7 +1758,7 @@ body: | ... --- name: test_undef3 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1784,7 +1784,7 @@ body: | ... --- name: test_undef4 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -1830,7 +1830,7 @@ body: | ... --- name: test_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: false tracksRegLiveness: true @@ -1910,7 +1910,7 @@ body: | ... --- name: test_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: false tracksRegLiveness: true @@ -1986,7 +1986,7 @@ body: | ... --- name: test_fpext -alignment: 4 +alignment: 16 legalized: true regBankSelected: false registers: @@ -2020,7 +2020,7 @@ body: | ... --- name: test_fptrunc -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2077,7 +2077,7 @@ body: | ... --- name: int32_to_float -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2111,7 +2111,7 @@ body: | ... --- name: int64_to_float -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2145,7 +2145,7 @@ body: | ... --- name: int32_to_double -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2179,7 +2179,7 @@ body: | ... --- name: int64_to_double -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2213,7 +2213,7 @@ body: | ... --- name: float_to_int8 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2251,7 +2251,7 @@ body: | ... --- name: float_to_int16 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2289,7 +2289,7 @@ body: | ... --- name: float_to_int32 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2323,7 +2323,7 @@ body: | ... --- name: float_to_int64 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2357,7 +2357,7 @@ body: | ... --- name: double_to_int8 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2395,7 +2395,7 @@ body: | ... --- name: double_to_int16 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2433,7 +2433,7 @@ body: | ... --- name: double_to_int32 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2467,7 +2467,7 @@ body: | ... --- name: double_to_int64 -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2501,7 +2501,7 @@ body: | ... --- name: fcmp_float_oeq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2548,7 +2548,7 @@ body: | ... --- name: fcmp_float_ogt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2595,7 +2595,7 @@ body: | ... --- name: fcmp_float_oge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2642,7 +2642,7 @@ body: | ... --- name: fcmp_float_olt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2689,7 +2689,7 @@ body: | ... --- name: fcmp_float_ole -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2736,7 +2736,7 @@ body: | ... --- name: fcmp_float_one -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2783,7 +2783,7 @@ body: | ... --- name: fcmp_float_ord -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2830,7 +2830,7 @@ body: | ... --- name: fcmp_float_uno -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2877,7 +2877,7 @@ body: | ... --- name: fcmp_float_ueq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2924,7 +2924,7 @@ body: | ... --- name: fcmp_float_ugt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -2971,7 +2971,7 @@ body: | ... --- name: fcmp_float_uge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3018,7 +3018,7 @@ body: | ... --- name: fcmp_float_ult -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3065,7 +3065,7 @@ body: | ... --- name: fcmp_float_ule -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3112,7 +3112,7 @@ body: | ... --- name: fcmp_float_une -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3159,7 +3159,7 @@ body: | ... --- name: fcmp_double_oeq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3206,7 +3206,7 @@ body: | ... --- name: fcmp_double_ogt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3253,7 +3253,7 @@ body: | ... --- name: fcmp_double_oge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3300,7 +3300,7 @@ body: | ... --- name: fcmp_double_olt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3347,7 +3347,7 @@ body: | ... --- name: fcmp_double_ole -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3394,7 +3394,7 @@ body: | ... --- name: fcmp_double_one -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3441,7 +3441,7 @@ body: | ... --- name: fcmp_double_ord -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3488,7 +3488,7 @@ body: | ... --- name: fcmp_double_uno -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3535,7 +3535,7 @@ body: | ... --- name: fcmp_double_ueq -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3582,7 +3582,7 @@ body: | ... --- name: fcmp_double_ugt -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3629,7 +3629,7 @@ body: | ... --- name: fcmp_double_uge -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3676,7 +3676,7 @@ body: | ... --- name: fcmp_double_ult -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3723,7 +3723,7 @@ body: | ... --- name: fcmp_double_ule -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: @@ -3770,7 +3770,7 @@ body: | ... --- name: fcmp_double_une -alignment: 4 +alignment: 16 legalized: true tracksRegLiveness: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir index d4fd6e29ab3..7d61e1c3f05 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir @@ -21,7 +21,7 @@ --- name: test_global_ptrv # CHECK-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -56,7 +56,7 @@ body: | --- name: test_global_valv # CHECK-LABEL: name: test_global_valv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir index 830251e3758..ce3f0ca611b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir @@ -21,7 +21,7 @@ --- name: test_global_ptrv # CHECK-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X64ALL: registers: @@ -54,7 +54,7 @@ body: | --- name: test_global_valv # CHECK-LABEL: name: test_global_valv -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X64ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir index 2584ff420e4..987f67bad15 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir @@ -28,7 +28,7 @@ --- name: test_add_v16i8 # ALL-LABEL: name: test_add_v16i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: @@ -70,7 +70,7 @@ body: | --- name: test_add_v8i16 # ALL-LABEL: name: test_add_v8i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: @@ -112,7 +112,7 @@ body: | --- name: test_add_v4i32 # ALL-LABEL: name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: @@ -154,7 +154,7 @@ body: | --- name: test_add_v2i64 # ALL-LABEL: name: test_add_v2i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NOVL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir index ea6bfa57628..3ee95929441 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir @@ -26,7 +26,7 @@ --- name: test_add_v32i8 # ALL-LABEL: name: test_add_v32i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -66,7 +66,7 @@ body: | --- name: test_add_v16i16 # ALL-LABEL: name: test_add_v16i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -106,7 +106,7 @@ body: | --- name: test_add_v8i32 # ALL-LABEL: name: test_add_v8i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: @@ -146,7 +146,7 @@ body: | --- name: test_add_v4i64 # ALL-LABEL: name: test_add_v4i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX2: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir index ce858fc79e5..c5498fda126 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir @@ -27,7 +27,7 @@ ... --- name: test_add_v64i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | ... --- name: test_add_v32i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -79,7 +79,7 @@ body: | ... --- name: test_add_v16i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -105,7 +105,7 @@ body: | ... --- name: test_add_v8i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir index e48853dc7d8..773813f19cd 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir @@ -9,7 +9,7 @@ ... --- name: test_add_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-add.mir b/llvm/test/CodeGen/X86/GlobalISel/select-add.mir index b4166a89e0a..d6e616109df 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-add.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-add.mir @@ -83,7 +83,7 @@ body: | --- name: test_add_i16 # ALL-LABEL: name: test_add_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -108,7 +108,7 @@ body: | --- name: test_add_i8 # ALL-LABEL: name: test_add_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -133,7 +133,7 @@ body: | --- name: test_add_v4i32 # ALL-LABEL: name: test_add_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -164,7 +164,7 @@ body: | --- name: test_add_v4f32 # ALL-LABEL: name: test_add_v4f32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir index 0f83b306b7d..d674e0b43fc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-and-scalar.mir @@ -25,7 +25,7 @@ ... --- name: test_and_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_and_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_and_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -115,7 +115,7 @@ body: | ... --- name: test_and_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir index ae051f99084..01efef5a705 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ashr-scalar.mir @@ -72,7 +72,7 @@ ... --- name: test_ashr_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -108,7 +108,7 @@ body: | ... --- name: test_ashr_i64_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -139,7 +139,7 @@ body: | ... --- name: test_ashr_i64_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -170,7 +170,7 @@ body: | ... --- name: test_ashr_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -206,7 +206,7 @@ body: | ... --- name: test_ashr_i32_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -237,7 +237,7 @@ body: | ... --- name: test_ashr_i32_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -268,7 +268,7 @@ body: | ... --- name: test_ashr_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -307,7 +307,7 @@ body: | ... --- name: test_ashr_i16_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -341,7 +341,7 @@ body: | ... --- name: test_ashr_i16_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -375,7 +375,7 @@ body: | ... --- name: test_ashr_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -414,7 +414,7 @@ body: | ... --- name: test_ashr_i8_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -448,7 +448,7 @@ body: | ... --- name: test_ashr_i8_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir index 752bd03f1f2..fe58606c2e9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir @@ -10,7 +10,7 @@ --- name: test_blsi32rr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -36,7 +36,7 @@ body: | ... --- name: test_blsi32rr_nomatch -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir b/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir index d6d095e366c..b1a30fbce06 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir @@ -7,7 +7,7 @@ --- name: test_blsr32rr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -33,7 +33,7 @@ body: | ... --- name: test_blsr32rr_nomatch -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-br.mir b/llvm/test/CodeGen/X86/GlobalISel/select-br.mir index 4872fb70c95..d28fa574238 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-br.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-br.mir @@ -17,7 +17,7 @@ --- name: uncondbr # CHECK-LABEL: name: uncondbr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # CHECK: JMP_1 %bb.2 diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir b/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir index 1906a00e12e..d21af414edb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir @@ -19,7 +19,7 @@ --- name: test # CHECK-LABEL: name: test -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir index ad106b000e8..2ff1fcba561 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir @@ -83,7 +83,7 @@ ... --- name: test_icmp_eq_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -114,7 +114,7 @@ body: | ... --- name: test_icmp_eq_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -145,7 +145,7 @@ body: | ... --- name: test_icmp_eq_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -176,7 +176,7 @@ body: | ... --- name: test_icmp_eq_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -207,7 +207,7 @@ body: | ... --- name: test_icmp_ne_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -238,7 +238,7 @@ body: | ... --- name: test_icmp_ugt_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -269,7 +269,7 @@ body: | ... --- name: test_icmp_uge_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -300,7 +300,7 @@ body: | ... --- name: test_icmp_ult_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -331,7 +331,7 @@ body: | ... --- name: test_icmp_ule_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -362,7 +362,7 @@ body: | ... --- name: test_icmp_sgt_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -393,7 +393,7 @@ body: | ... --- name: test_icmp_sge_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -424,7 +424,7 @@ body: | ... --- name: test_icmp_slt_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -455,7 +455,7 @@ body: | ... --- name: test_icmp_sle_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir index 08c8b67e514..33c561f8865 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-constant.mir @@ -127,7 +127,7 @@ body: | ... --- name: const_i64_u32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -164,7 +164,7 @@ body: | ... --- name: main -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir index 5e36ffa6fc5..cb6948a16cb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-copy.mir @@ -31,7 +31,7 @@ --- name: test_copy # ALL-LABEL: name: test_copy -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -57,7 +57,7 @@ body: | --- name: test_copy2 # ALL-LABEL: name: test_copy2 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -83,7 +83,7 @@ body: | --- name: test_copy3 # ALL-LABEL: name: test_copy3 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -113,7 +113,7 @@ body: | --- name: test_copy4 # ALL-LABEL: name: test_copy4 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -143,7 +143,7 @@ body: | --- name: test_copy5 # ALL-LABEL: name: test_copy5 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -173,7 +173,7 @@ body: | --- name: test_copy6 # ALL-LABEL: name: test_copy6 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir index 3c61ff623d8..4eb2d5b148a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir @@ -25,7 +25,7 @@ ... --- name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -51,7 +51,7 @@ body: | ... --- name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -74,7 +74,7 @@ body: | ... --- name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -97,7 +97,7 @@ body: | ... --- name: anyext_s64_from_s1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -122,7 +122,7 @@ body: | ... --- name: anyext_s64_from_s8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -148,7 +148,7 @@ body: | ... --- name: anyext_s64_from_s16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -174,7 +174,7 @@ body: | ... --- name: anyext_s64_from_s32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir index ce3e7900731..b236ba24800 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-ext.mir @@ -48,7 +48,7 @@ --- name: test_zext_i1toi8 # ALL-LABEL: name: test_zext_i1toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -84,7 +84,7 @@ body: | --- name: test_zext_i1toi16 # ALL-LABEL: name: test_zext_i1toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -123,7 +123,7 @@ body: | --- name: test_zext_i1 # ALL-LABEL: name: test_zext_i1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -162,7 +162,7 @@ body: | --- name: test_zext_i8 # ALL-LABEL: name: test_zext_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -188,7 +188,7 @@ body: | --- name: test_zext_i16 # ALL-LABEL: name: test_zext_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -214,7 +214,7 @@ body: | --- name: test_sext_i8 # ALL-LABEL: name: test_sext_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -240,7 +240,7 @@ body: | --- name: test_sext_i16 # ALL-LABEL: name: test_sext_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -266,7 +266,7 @@ body: | --- name: test_anyext_i1toi8 # ALL-LABEL: name: test_anyext_i1toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -300,7 +300,7 @@ body: | --- name: test_anyext_i1toi16 # ALL-LABEL: name: test_anyext_i1toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -335,7 +335,7 @@ body: | --- name: test_anyext_i1toi32 # ALL-LABEL: name: test_anyext_i1toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -370,7 +370,7 @@ body: | --- name: test_anyext_i8toi16 # ALL-LABEL: name: test_anyext_i8toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -405,7 +405,7 @@ body: | --- name: test_anyext_i8toi32 # ALL-LABEL: name: test_anyext_i8toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # X32: registers: @@ -440,7 +440,7 @@ body: | --- name: test_anyext_i16toi32 # ALL-LABEL: name: test_anyext_i16toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir index 06f58643008..36a9244fe54 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec256.mir @@ -14,7 +14,7 @@ --- name: test_extract_128_idx0 # ALL-LABEL: name: test_extract_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX: registers: @@ -46,7 +46,7 @@ body: | --- name: test_extract_128_idx1 # ALL-LABEL: name: test_extract_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # AVX: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir index 7203b9e6971..f0491b6e0d8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-extract-vec512.mir @@ -23,7 +23,7 @@ --- name: test_extract_128_idx0 # ALL-LABEL: name: test_extract_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -49,7 +49,7 @@ body: | --- name: test_extract_128_idx1 # ALL-LABEL: name: test_extract_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -75,7 +75,7 @@ body: | --- name: test_extract_256_idx0 # ALL-LABEL: name: test_extract_256_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: @@ -101,7 +101,7 @@ body: | --- name: test_extract_256_idx1 # ALL-LABEL: name: test_extract_256_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir index 931fd4f7c2c..a34f622db1b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fadd_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fadd_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir index d3ee1b3c4f8..47be0d593e8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fconstant.mir @@ -18,7 +18,7 @@ --- name: test_float # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -63,7 +63,7 @@ body: | --- name: test_double # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir index bd36a8e0626..8741968a5da 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fdiv-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fdiv_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fdiv_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir index 326762d9cf9..826e70dea2d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fmul-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fmul_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fmul_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir index cd72edd729a..97edc58e69d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fpext-scalar.mir @@ -11,7 +11,7 @@ ... --- name: test -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir index 3b259729ce8..bb6c1e9930d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fptrunc-scalar.mir @@ -10,7 +10,7 @@ ... --- name: test_fptrunc -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir index 6564f77a261..efc6cd57115 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-fsub-scalar.mir @@ -18,7 +18,7 @@ ... --- name: test_fsub_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # @@ -87,7 +87,7 @@ body: | ... --- name: test_fsub_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir b/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir index ce54b5e405e..0b90620107f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-gep.mir @@ -9,7 +9,7 @@ ... --- name: test_gep_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir index 685596d5904..9424e1d52b7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec256.mir @@ -21,7 +21,7 @@ --- name: test_insert_128_idx0 # ALL-LABEL: name: test_insert_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | --- name: test_insert_128_idx0_undef # ALL-LABEL: name: test_insert_128_idx0_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -83,7 +83,7 @@ body: | --- name: test_insert_128_idx1 # ALL-LABEL: name: test_insert_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -114,7 +114,7 @@ body: | --- name: test_insert_128_idx1_undef # ALL-LABEL: name: test_insert_128_idx1_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir index d3bd3b70920..fefce0bc17c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-insert-vec512.mir @@ -37,7 +37,7 @@ ... --- name: test_insert_128_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -63,7 +63,7 @@ body: | ... --- name: test_insert_128_idx0_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -88,7 +88,7 @@ body: | ... --- name: test_insert_128_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -113,7 +113,7 @@ body: | ... --- name: test_insert_128_idx1_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -138,7 +138,7 @@ body: | ... --- name: test_insert_256_idx0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -164,7 +164,7 @@ body: | ... --- name: test_insert_256_idx0_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -189,7 +189,7 @@ body: | ... --- name: test_insert_256_idx1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -214,7 +214,7 @@ body: | ... --- name: test_insert_256_idx1_undef -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir index c20243d0c28..4478ef5a5fc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-lshr-scalar.mir @@ -72,7 +72,7 @@ ... --- name: test_lshr_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -108,7 +108,7 @@ body: | ... --- name: test_lshr_i64_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -139,7 +139,7 @@ body: | ... --- name: test_lshr_i64_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -170,7 +170,7 @@ body: | ... --- name: test_lshr_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -206,7 +206,7 @@ body: | ... --- name: test_lshr_i32_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -237,7 +237,7 @@ body: | ... --- name: test_lshr_i32_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -268,7 +268,7 @@ body: | ... --- name: test_lshr_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -307,7 +307,7 @@ body: | ... --- name: test_lshr_i16_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -341,7 +341,7 @@ body: | ... --- name: test_lshr_i16_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -375,7 +375,7 @@ body: | ... --- name: test_lshr_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -414,7 +414,7 @@ body: | ... --- name: test_lshr_i8_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -448,7 +448,7 @@ body: | ... --- name: test_lshr_i8_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir index 70b1a2dfc5c..d9016f907d1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-unordered.mir @@ -101,7 +101,7 @@ ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -139,7 +139,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -177,7 +177,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -215,7 +215,7 @@ body: | ... --- name: test_load_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -253,7 +253,7 @@ body: | ... --- name: test_load_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -303,7 +303,7 @@ body: | ... --- name: test_load_float_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -353,7 +353,7 @@ body: | ... --- name: test_load_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -403,7 +403,7 @@ body: | ... --- name: test_load_double_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -453,7 +453,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -496,7 +496,7 @@ body: | ... --- name: test_store_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -539,7 +539,7 @@ body: | ... --- name: test_store_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -594,7 +594,7 @@ body: | ... --- name: test_store_float_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -649,7 +649,7 @@ body: | ... --- name: test_store_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -705,7 +705,7 @@ body: | ... --- name: test_store_double_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -760,7 +760,7 @@ body: | ... --- name: test_load_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -799,7 +799,7 @@ body: | ... --- name: test_store_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -838,7 +838,7 @@ body: | ... --- name: test_gep_folding -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -891,7 +891,7 @@ body: | ... --- name: test_gep_folding_largeGepIndex -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir index e940a462f07..78be9d573ea 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir @@ -45,7 +45,7 @@ ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -70,7 +70,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -95,7 +95,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -120,7 +120,7 @@ body: | ... --- name: test_store_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -150,7 +150,7 @@ body: | ... --- name: test_store_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -180,7 +180,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -210,7 +210,7 @@ body: | ... --- name: test_load_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -235,7 +235,7 @@ body: | ... --- name: test_store_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir index f366bf33683..a552e5658f1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir @@ -101,7 +101,7 @@ ... --- name: test_load_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -139,7 +139,7 @@ body: | ... --- name: test_load_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -177,7 +177,7 @@ body: | ... --- name: test_load_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -215,7 +215,7 @@ body: | ... --- name: test_load_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -253,7 +253,7 @@ body: | ... --- name: test_load_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -303,7 +303,7 @@ body: | ... --- name: test_load_float_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -353,7 +353,7 @@ body: | ... --- name: test_load_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -403,7 +403,7 @@ body: | ... --- name: test_load_double_vecreg -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -453,7 +453,7 @@ body: | ... --- name: test_store_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -496,7 +496,7 @@ body: | ... --- name: test_store_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -539,7 +539,7 @@ body: | ... --- name: test_store_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -594,7 +594,7 @@ body: | ... --- name: test_store_float_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -649,7 +649,7 @@ body: | ... --- name: test_store_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -705,7 +705,7 @@ body: | ... --- name: test_store_double_vec -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -760,7 +760,7 @@ body: | ... --- name: test_load_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -799,7 +799,7 @@ body: | ... --- name: test_store_ptr -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -838,7 +838,7 @@ body: | ... --- name: test_gep_folding -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -891,7 +891,7 @@ body: | ... --- name: test_gep_folding_largeGepIndex -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir index 84c8d084edc..8b04d5e191c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir @@ -28,7 +28,7 @@ --- # ALL-LABEL: name: test_load_v4i32_noalign name: test_load_v4i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | --- # ALL-LABEL: name: test_load_v4i32_align name: test_load_v4i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -78,7 +78,7 @@ body: | --- # ALL-LABEL: name: test_store_v4i32_align name: test_store_v4i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -106,7 +106,7 @@ body: | --- # ALL-LABEL: name: test_store_v4i32_noalign name: test_store_v4i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir index 4863be2a63e..e1369a60d50 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir @@ -29,7 +29,7 @@ --- name: test_load_v8i32_noalign # ALL-LABEL: name: test_load_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: @@ -69,7 +69,7 @@ body: | --- name: test_load_v8i32_align # ALL-LABEL: name: test_load_v8i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -102,7 +102,7 @@ body: | --- name: test_store_v8i32_noalign # ALL-LABEL: name: test_store_v8i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: @@ -142,7 +142,7 @@ body: | --- name: test_store_v8i32_align # ALL-LABEL: name: test_store_v8i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # NO_AVX512F: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir index 0de858e55a1..a9175592261 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir @@ -24,7 +24,7 @@ ... --- name: test_load_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -47,7 +47,7 @@ body: | ... --- name: test_load_v16i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -70,7 +70,7 @@ body: | ... --- name: test_store_v16i32_noalign -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -93,7 +93,7 @@ body: | ... --- name: test_store_v16i32_align -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir index ab7532f0e0a..8c04cc6f76c 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir @@ -9,7 +9,7 @@ --- name: test_merge # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir index d188d3ef9ad..3c003d6cf92 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec512.mir @@ -12,7 +12,7 @@ ... --- name: test_merge_v128 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -37,7 +37,7 @@ body: | ... --- name: test_merge_v256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir index d90c4615377..826fb26cb07 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir @@ -20,7 +20,7 @@ ... --- name: test_mul_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -46,7 +46,7 @@ body: | ... --- name: test_mul_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -72,7 +72,7 @@ body: | ... --- name: test_mul_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir b/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir index 3eb963e419b..215926b030b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir @@ -91,7 +91,7 @@ ... --- name: test_mul_v8i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -117,7 +117,7 @@ body: | ... --- name: test_mul_v8i16_avx -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -143,7 +143,7 @@ body: | ... --- name: test_mul_v8i16_avx512bwvl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -169,7 +169,7 @@ body: | ... --- name: test_mul_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -195,7 +195,7 @@ body: | ... --- name: test_mul_v4i32_avx -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -221,7 +221,7 @@ body: | ... --- name: test_mul_v4i32_avx512vl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -247,7 +247,7 @@ body: | ... --- name: test_mul_v2i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -273,7 +273,7 @@ body: | ... --- name: test_mul_v16i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -299,7 +299,7 @@ body: | ... --- name: test_mul_v16i16_avx512bwvl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -325,7 +325,7 @@ body: | ... --- name: test_mul_v8i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -351,7 +351,7 @@ body: | ... --- name: test_mul_v8i32_avx512vl -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -377,7 +377,7 @@ body: | ... --- name: test_mul_v4i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -403,7 +403,7 @@ body: | ... --- name: test_mul_v32i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -429,7 +429,7 @@ body: | ... --- name: test_mul_v16i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -455,7 +455,7 @@ body: | ... --- name: test_mul_v8i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir index 832c38dc159..2c13c0afe3e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-or-scalar.mir @@ -25,7 +25,7 @@ ... --- name: test_or_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_or_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_or_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -115,7 +115,7 @@ body: | ... --- name: test_or_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir index 4323288fe1b..ef70ef5d924 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-phi.mir @@ -102,7 +102,7 @@ ... --- name: test_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -161,7 +161,7 @@ body: | ... --- name: test_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -220,7 +220,7 @@ body: | ... --- name: test_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -283,7 +283,7 @@ body: | ... --- name: test_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -346,7 +346,7 @@ body: | ... --- name: test_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -411,7 +411,7 @@ body: | ... --- name: test_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir index 1c4dcf4a334..1928093b04d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-shl-scalar.mir @@ -73,7 +73,7 @@ ... --- name: test_shl_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -109,7 +109,7 @@ body: | ... --- name: test_shl_i64_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -140,7 +140,7 @@ body: | ... --- name: test_shl_i64_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -171,7 +171,7 @@ body: | ... --- name: test_shl_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -207,7 +207,7 @@ body: | ... --- name: test_shl_i32_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -238,7 +238,7 @@ body: | ... --- name: test_shl_i32_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -269,7 +269,7 @@ body: | ... --- name: test_shl_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -308,7 +308,7 @@ body: | ... --- name: test_shl_i16_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -342,7 +342,7 @@ body: | ... --- name: test_shl_i16_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -376,7 +376,7 @@ body: | ... --- name: test_shl_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -415,7 +415,7 @@ body: | ... --- name: test_shl_i8_imm -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -449,7 +449,7 @@ body: | ... --- name: test_shl_i8_imm1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir index d9c5ccdf72f..db1cf8183aa 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir @@ -28,7 +28,7 @@ --- name: test_sub_v16i8 # ALL-LABEL: name: test_sub_v16i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -56,7 +56,7 @@ body: | --- name: test_sub_v8i16 # ALL-LABEL: name: test_sub_v8i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -84,7 +84,7 @@ body: | --- name: test_sub_v4i32 # ALL-LABEL: name: test_sub_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -112,7 +112,7 @@ body: | --- name: test_sub_v2i64 # ALL-LABEL: name: test_sub_v2i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir index ae1ae9b1eee..6959dfe6382 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir @@ -26,7 +26,7 @@ --- name: test_sub_v32i8 # ALL-LABEL: name: test_sub_v32i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -52,7 +52,7 @@ body: | --- name: test_sub_v16i16 # ALL-LABEL: name: test_sub_v16i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -78,7 +78,7 @@ body: | --- name: test_sub_v8i32 # ALL-LABEL: name: test_sub_v8i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -104,7 +104,7 @@ body: | --- name: test_sub_v4i64 # ALL-LABEL: name: test_sub_v4i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir index 3e1772a7894..52a948211b2 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir @@ -27,7 +27,7 @@ ... --- name: test_sub_v64i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -53,7 +53,7 @@ body: | ... --- name: test_sub_v32i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -79,7 +79,7 @@ body: | ... --- name: test_sub_v16i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -105,7 +105,7 @@ body: | ... --- name: test_sub_v8i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir b/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir index 33aa64463c8..1f46b02082a 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-sub.mir @@ -70,7 +70,7 @@ body: | ... --- name: test_sub_v4i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false @@ -100,7 +100,7 @@ body: | ... --- name: test_sub_v4f32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true selected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir index 68d2bb119f4..08943172487 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir @@ -34,7 +34,7 @@ ... --- name: trunc_i32toi1 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -59,7 +59,7 @@ body: | ... --- name: trunc_i32toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -82,7 +82,7 @@ body: | ... --- name: trunc_i32toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -105,7 +105,7 @@ body: | ... --- name: trunc_i64toi8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -128,7 +128,7 @@ body: | ... --- name: trunc_i64toi16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -151,7 +151,7 @@ body: | ... --- name: trunc_i64toi32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir b/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir index ec9a970a31b..dddebf209bf 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-undef.mir @@ -17,7 +17,7 @@ ... --- name: test -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -39,7 +39,7 @@ body: | ... --- name: test2 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -69,7 +69,7 @@ body: | ... --- name: test3 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir index bc1f707cafe..39471928d44 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec256.mir @@ -10,7 +10,7 @@ --- name: test_unmerge # -alignment: 4 +alignment: 16 legalized: true regBankSelected: true # diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir index 2b96ed12dfa..17730f985f9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-unmerge-vec512.mir @@ -12,7 +12,7 @@ ... --- name: test_unmerge_v128 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -40,7 +40,7 @@ body: | ... --- name: test_unmerge_v256 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir b/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir index 2e9fb6a7b85..30d214607f0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/select-xor-scalar.mir @@ -25,7 +25,7 @@ ... --- name: test_xor_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -55,7 +55,7 @@ body: | ... --- name: test_xor_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -85,7 +85,7 @@ body: | ... --- name: test_xor_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: @@ -115,7 +115,7 @@ body: | ... --- name: test_xor_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir index a131f1f3220..d4f785dfee8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-GV.mir @@ -11,7 +11,7 @@ --- name: test_global_ptrv # ALL-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir index 83079632b10..67ed879723b 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir index 8db6b0f47b0..86879866f10 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-ptrtoint.mir @@ -30,7 +30,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -60,7 +60,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -87,7 +87,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -114,7 +114,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir index f36e73640f1..80382db9427 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir @@ -24,7 +24,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -56,7 +56,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -88,7 +88,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir index 13174eab502..466990bf7f8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir @@ -25,7 +25,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -87,7 +87,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -149,7 +149,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir index d4b78de113d..85c9b6d9e86 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir @@ -24,7 +24,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -83,7 +83,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -142,7 +142,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir index b2213ab5b73..77ff45293fb 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir @@ -25,7 +25,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -87,7 +87,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -149,7 +149,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir index 2fcdb200730..6b740a18c14 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir index 90e71db9e8b..38ce2160b58 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir @@ -30,7 +30,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -60,7 +60,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -88,7 +88,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -116,7 +116,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir index 99781b603aa..25904de22ba 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-sdiv.mir @@ -24,7 +24,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -60,7 +60,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -97,7 +97,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir index 164d53ea79d..93bab680ee9 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-srem.mir @@ -25,7 +25,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -87,7 +87,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -150,7 +150,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir index bd181fb5f00..ea548c296dc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir @@ -15,7 +15,7 @@ ... --- name: trap -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir index 7eff94478b2..b36c17fe8b3 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir @@ -25,7 +25,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -87,7 +87,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -151,7 +151,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir index 10d07daca88..fe97a2bcb39 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86-select-urem.mir @@ -25,7 +25,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -87,7 +87,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -151,7 +151,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir index 01c9f49e106..95cc0d90c75 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir @@ -11,7 +11,7 @@ --- name: test_global_ptrv # ALL-LABEL: name: test_global_ptrv -alignment: 4 +alignment: 16 legalized: false regBankSelected: false # ALL: registers: diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir index c4083184b41..4eabd9a4c1e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fcmp.mir @@ -146,7 +146,7 @@ ... --- name: fcmp_float_oeq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -181,7 +181,7 @@ body: | ... --- name: fcmp_float_ogt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -216,7 +216,7 @@ body: | ... --- name: fcmp_float_oge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -251,7 +251,7 @@ body: | ... --- name: fcmp_float_olt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -286,7 +286,7 @@ body: | ... --- name: fcmp_float_ole -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -321,7 +321,7 @@ body: | ... --- name: fcmp_float_one -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -356,7 +356,7 @@ body: | ... --- name: fcmp_float_ord -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -391,7 +391,7 @@ body: | ... --- name: fcmp_float_uno -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -426,7 +426,7 @@ body: | ... --- name: fcmp_float_ueq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -461,7 +461,7 @@ body: | ... --- name: fcmp_float_ugt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -496,7 +496,7 @@ body: | ... --- name: fcmp_float_uge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -531,7 +531,7 @@ body: | ... --- name: fcmp_float_ult -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -566,7 +566,7 @@ body: | ... --- name: fcmp_float_ule -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -601,7 +601,7 @@ body: | ... --- name: fcmp_float_une -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -636,7 +636,7 @@ body: | ... --- name: fcmp_double_oeq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -671,7 +671,7 @@ body: | ... --- name: fcmp_double_ogt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -706,7 +706,7 @@ body: | ... --- name: fcmp_double_oge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -741,7 +741,7 @@ body: | ... --- name: fcmp_double_olt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -776,7 +776,7 @@ body: | ... --- name: fcmp_double_ole -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -811,7 +811,7 @@ body: | ... --- name: fcmp_double_one -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -846,7 +846,7 @@ body: | ... --- name: fcmp_double_ord -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -881,7 +881,7 @@ body: | ... --- name: fcmp_double_uno -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -916,7 +916,7 @@ body: | ... --- name: fcmp_double_ueq -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -951,7 +951,7 @@ body: | ... --- name: fcmp_double_ugt -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -986,7 +986,7 @@ body: | ... --- name: fcmp_double_uge -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1021,7 +1021,7 @@ body: | ... --- name: fcmp_double_ult -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1056,7 +1056,7 @@ body: | ... --- name: fcmp_double_ule -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -1091,7 +1091,7 @@ body: | ... --- name: fcmp_double_une -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir index 194b2a77666..5d244d4a9c0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-fptosi.mir @@ -54,7 +54,7 @@ ... --- name: float_to_int8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -81,7 +81,7 @@ body: | ... --- name: float_to_int16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -108,7 +108,7 @@ body: | ... --- name: float_to_int32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -134,7 +134,7 @@ body: | ... --- name: float_to_int64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -160,7 +160,7 @@ body: | ... --- name: double_to_int8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -187,7 +187,7 @@ body: | ... --- name: double_to_int16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -214,7 +214,7 @@ body: | ... --- name: double_to_int32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -240,7 +240,7 @@ body: | ... --- name: double_to_int64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir index 361e39b6e8f..90aed846b95 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir index 6e46ae2a785..3dc342e6ee0 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-ptrtoint.mir @@ -36,7 +36,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -62,7 +62,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -85,7 +85,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -108,7 +108,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -131,7 +131,7 @@ body: | ... --- name: ptrtoint_s64_p0 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir index 5314c91fe03..faccc3750c8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sdiv.mir @@ -29,7 +29,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -61,7 +61,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -93,7 +93,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -119,7 +119,7 @@ body: | ... --- name: test_sdiv_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir index 7a69731652d..5713ddf22d4 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-sitofp.mir @@ -74,7 +74,7 @@ ... --- name: int8_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -108,7 +108,7 @@ body: | ... --- name: int16_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -142,7 +142,7 @@ body: | ... --- name: int32_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -168,7 +168,7 @@ body: | ... --- name: int64_to_float -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -194,7 +194,7 @@ body: | ... --- name: int8_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -228,7 +228,7 @@ body: | ... --- name: int16_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -262,7 +262,7 @@ body: | ... --- name: int32_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -288,7 +288,7 @@ body: | ... --- name: int64_to_double -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir index 67787cc854b..f02442f2b85 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir @@ -29,7 +29,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -88,7 +88,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -147,7 +147,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -200,7 +200,7 @@ body: | ... --- name: test_srem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir index 027c1112801..35073e2bcb1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir @@ -29,7 +29,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -88,7 +88,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -147,7 +147,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -200,7 +200,7 @@ body: | ... --- name: test_udiv_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir index 35e5366b1d9..c0ca5ae74fc 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir @@ -29,7 +29,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -88,7 +88,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -147,7 +147,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -200,7 +200,7 @@ body: | ... --- name: test_urem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir index 834f214ad07..0795539e7c1 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-legalize-zext.mir @@ -56,7 +56,7 @@ ... --- name: zext_i1_to_i8 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -83,7 +83,7 @@ body: | ... --- name: zext_i1_to_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -110,7 +110,7 @@ body: | ... --- name: zext_i1_to_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -137,7 +137,7 @@ body: | ... --- name: zext_i1_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -164,7 +164,7 @@ body: | ... --- name: zext_i8_to_i16 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -191,7 +191,7 @@ body: | ... --- name: zext_i8_to_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -218,7 +218,7 @@ body: | ... --- name: zext_i8_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -245,7 +245,7 @@ body: | ... --- name: zext_i16_to_i32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -272,7 +272,7 @@ body: | ... --- name: zext_i16_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } @@ -299,7 +299,7 @@ body: | ... --- name: zext_i32_to_i64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: _ } diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir index 9c0396db899..e60720cfa87 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir @@ -146,7 +146,7 @@ ... --- name: fcmp_float_oeq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -186,7 +186,7 @@ body: | ... --- name: fcmp_float_ogt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -224,7 +224,7 @@ body: | ... --- name: fcmp_float_oge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -262,7 +262,7 @@ body: | ... --- name: fcmp_float_olt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -300,7 +300,7 @@ body: | ... --- name: fcmp_float_ole -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -338,7 +338,7 @@ body: | ... --- name: fcmp_float_one -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -376,7 +376,7 @@ body: | ... --- name: fcmp_float_ord -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -414,7 +414,7 @@ body: | ... --- name: fcmp_float_uno -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -452,7 +452,7 @@ body: | ... --- name: fcmp_float_ueq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -490,7 +490,7 @@ body: | ... --- name: fcmp_float_ugt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -528,7 +528,7 @@ body: | ... --- name: fcmp_float_uge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -566,7 +566,7 @@ body: | ... --- name: fcmp_float_ult -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -604,7 +604,7 @@ body: | ... --- name: fcmp_float_ule -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -642,7 +642,7 @@ body: | ... --- name: fcmp_float_une -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -682,7 +682,7 @@ body: | ... --- name: fcmp_double_oeq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -722,7 +722,7 @@ body: | ... --- name: fcmp_double_ogt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -760,7 +760,7 @@ body: | ... --- name: fcmp_double_oge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -798,7 +798,7 @@ body: | ... --- name: fcmp_double_olt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -836,7 +836,7 @@ body: | ... --- name: fcmp_double_ole -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -874,7 +874,7 @@ body: | ... --- name: fcmp_double_one -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -912,7 +912,7 @@ body: | ... --- name: fcmp_double_ord -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -950,7 +950,7 @@ body: | ... --- name: fcmp_double_uno -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -988,7 +988,7 @@ body: | ... --- name: fcmp_double_ueq -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1026,7 +1026,7 @@ body: | ... --- name: fcmp_double_ugt -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1064,7 +1064,7 @@ body: | ... --- name: fcmp_double_uge -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1102,7 +1102,7 @@ body: | ... --- name: fcmp_double_ult -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1140,7 +1140,7 @@ body: | ... --- name: fcmp_double_ule -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -1178,7 +1178,7 @@ body: | ... --- name: fcmp_double_une -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir index b5085d59be8..6ff271d487e 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-fptosi.mir @@ -54,7 +54,7 @@ ... --- name: float_to_int8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -85,7 +85,7 @@ body: | ... --- name: float_to_int16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -116,7 +116,7 @@ body: | ... --- name: float_to_int32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -144,7 +144,7 @@ body: | ... --- name: float_to_int64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -172,7 +172,7 @@ body: | ... --- name: double_to_int8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -203,7 +203,7 @@ body: | ... --- name: double_to_int16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -234,7 +234,7 @@ body: | ... --- name: double_to_int32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -262,7 +262,7 @@ body: | ... --- name: double_to_int64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir index 33766abe4c4..f9ce11e48f7 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-inttoptr.mir @@ -12,7 +12,7 @@ ... --- name: inttoptr_p0_s64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir index 94027c41212..4f330f6119f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-ptrtoint.mir @@ -36,7 +36,7 @@ ... --- name: ptrtoint_s1_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -63,7 +63,7 @@ body: | ... --- name: ptrtoint_s8_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -88,7 +88,7 @@ body: | ... --- name: ptrtoint_s16_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -113,7 +113,7 @@ body: | ... --- name: ptrtoint_s32_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -138,7 +138,7 @@ body: | ... --- name: ptrtoint_s64_p0 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir index 68f21c8ea7d..d3a1608be52 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir @@ -29,7 +29,7 @@ ... --- name: test_sdiv_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -65,7 +65,7 @@ body: | ... --- name: test_sdiv_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -102,7 +102,7 @@ body: | ... --- name: test_sdiv_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -133,7 +133,7 @@ body: | ... --- name: test_sdiv_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir index eeb976cae38..f853fe7bbb3 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-sitofp.mir @@ -46,7 +46,7 @@ ... --- name: int32_to_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -74,7 +74,7 @@ body: | ... --- name: int64_to_float -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -102,7 +102,7 @@ body: | ... --- name: int32_to_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -130,7 +130,7 @@ body: | ... --- name: int64_to_double -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir index 53c444e327e..a0551f1f59d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir @@ -29,7 +29,7 @@ ... --- name: test_srem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -90,7 +90,7 @@ body: | ... --- name: test_srem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -152,7 +152,7 @@ body: | ... --- name: test_srem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -208,7 +208,7 @@ body: | ... --- name: test_srem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir index 44b057cbf32..71c03fd6e28 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir @@ -29,7 +29,7 @@ ... --- name: test_udiv_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -90,7 +90,7 @@ body: | ... --- name: test_udiv_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -153,7 +153,7 @@ body: | ... --- name: test_udiv_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -210,7 +210,7 @@ body: | ... --- name: test_udiv_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir index 3fa33e6f34a..c25db2b6f0f 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir @@ -29,7 +29,7 @@ ... --- name: test_urem_i8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -90,7 +90,7 @@ body: | ... --- name: test_urem_i16 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -153,7 +153,7 @@ body: | ... --- name: test_urem_i32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true @@ -210,7 +210,7 @@ body: | ... --- name: test_urem_i64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir index b0b445de800..c1a339422c8 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir +++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir @@ -56,7 +56,7 @@ ... --- name: zext_i1_to_i8 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -87,7 +87,7 @@ body: | ... --- name: zext_i1_to_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -118,7 +118,7 @@ body: | ... --- name: zext_i1_to_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -148,7 +148,7 @@ body: | ... --- name: zext_i1_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -180,7 +180,7 @@ body: | ... --- name: zext_i8_to_i16 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -211,7 +211,7 @@ body: | ... --- name: zext_i8_to_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -242,7 +242,7 @@ body: | ... --- name: zext_i8_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -274,7 +274,7 @@ body: | ... --- name: zext_i16_to_i32 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -305,7 +305,7 @@ body: | ... --- name: zext_i16_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true @@ -337,7 +337,7 @@ body: | ... --- name: zext_i32_to_i64 -alignment: 4 +alignment: 16 legalized: true regBankSelected: true tracksRegLiveness: true diff --git a/llvm/test/CodeGen/X86/PR37310.mir b/llvm/test/CodeGen/X86/PR37310.mir index c35462bb8ae..05e3f2c561f 100644 --- a/llvm/test/CodeGen/X86/PR37310.mir +++ b/llvm/test/CodeGen/X86/PR37310.mir @@ -64,7 +64,7 @@ ... --- name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/adx-commute.mir b/llvm/test/CodeGen/X86/adx-commute.mir index 1e204e33913..e2023c12293 100644 --- a/llvm/test/CodeGen/X86/adx-commute.mir +++ b/llvm/test/CodeGen/X86/adx-commute.mir @@ -54,7 +54,7 @@ ... --- name: adcx32_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -99,7 +99,7 @@ body: | ... --- name: adcx64_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -144,7 +144,7 @@ body: | ... --- name: adox32_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -189,7 +189,7 @@ body: | ... --- name: adox64_commute -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir index 82cb9a786c2..c90c2f05b4f 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir @@ -95,7 +95,7 @@ ... --- name: debug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -153,7 +153,7 @@ body: | ... --- name: nodebug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir index c14d0f6c25b..17b6b8744be 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir @@ -106,7 +106,7 @@ ... --- name: debug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir index 3ae44db4f75..3290ab9017a 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir @@ -122,7 +122,7 @@ ... --- name: debug -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir b/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir index cfddb1f0b8b..9ae885c94c6 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir @@ -28,7 +28,7 @@ ... --- name: test_imm_store -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/avoid-sfb-offset.mir b/llvm/test/CodeGen/X86/avoid-sfb-offset.mir index 659f1a0923e..027cc399f0f 100644 --- a/llvm/test/CodeGen/X86/avoid-sfb-offset.mir +++ b/llvm/test/CodeGen/X86/avoid-sfb-offset.mir @@ -35,7 +35,7 @@ ... --- name: test_offset -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/avx512f-256-set0.mir b/llvm/test/CodeGen/X86/avx512f-256-set0.mir index 45fbafae11d..de240a6f376 100644 --- a/llvm/test/CodeGen/X86/avx512f-256-set0.mir +++ b/llvm/test/CodeGen/X86/avx512f-256-set0.mir @@ -25,7 +25,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/bad-tls-fold.mir b/llvm/test/CodeGen/X86/bad-tls-fold.mir index 550d0db3cb0..597a83d8938 100644 --- a/llvm/test/CodeGen/X86/bad-tls-fold.mir +++ b/llvm/test/CodeGen/X86/bad-tls-fold.mir @@ -18,7 +18,7 @@ --- # CHECK-LABEL: or: name: or -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } @@ -48,7 +48,7 @@ body: | --- # CHECK-LABEL: and: name: and -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/block-placement.mir b/llvm/test/CodeGen/X86/block-placement.mir index 04444bea952..1d661687d25 100644 --- a/llvm/test/CodeGen/X86/block-placement.mir +++ b/llvm/test/CodeGen/X86/block-placement.mir @@ -40,7 +40,7 @@ --- # CHECK: name: f name: f -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } diff --git a/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir b/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir index d311bb2458d..aa6d317acc3 100644 --- a/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir +++ b/llvm/test/CodeGen/X86/conditional-tailcall-samedest.mir @@ -70,7 +70,7 @@ ... --- name: f -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir b/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir index f218c0c6477..e0412817a04 100644 --- a/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir +++ b/llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding2.mir @@ -83,7 +83,7 @@ # CHECK: bb.12.for.body.10 name: _Z3fn1v -alignment: 4 +alignment: 16 tracksRegLiveness: true constants: body: | diff --git a/llvm/test/CodeGen/X86/domain-reassignment.mir b/llvm/test/CodeGen/X86/domain-reassignment.mir index 9fa779d7653..38755344849 100644 --- a/llvm/test/CodeGen/X86/domain-reassignment.mir +++ b/llvm/test/CodeGen/X86/domain-reassignment.mir @@ -49,7 +49,7 @@ ... --- name: test_fcmp_storefloat -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -202,7 +202,7 @@ body: | ... --- name: test_8bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -323,7 +323,7 @@ body: | ... --- name: test_16bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -441,7 +441,7 @@ body: | ... --- name: test_32bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -544,7 +544,7 @@ body: | ... --- name: test_64bitops -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -647,7 +647,7 @@ body: | ... --- name: test_16bitext -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -716,7 +716,7 @@ body: | ... --- name: test_32bitext -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -789,7 +789,7 @@ body: | ... --- name: test_64bitext -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/fixup-bw-inst.mir b/llvm/test/CodeGen/X86/fixup-bw-inst.mir index fe39251d6e9..0f0b4545791 100644 --- a/llvm/test/CodeGen/X86/fixup-bw-inst.mir +++ b/llvm/test/CodeGen/X86/fixup-bw-inst.mir @@ -39,7 +39,7 @@ --- # CHECK-LABEL: name: test1 name: test1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rax' } @@ -61,7 +61,7 @@ body: | --- # CHECK-LABEL: name: test2 name: test2 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rax' } @@ -82,7 +82,7 @@ body: | --- # CHECK-LABEL: name: test3 name: test3 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -116,7 +116,7 @@ body: | --- # CHECK-LABEL: name: test4 name: test4 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$r9d' } @@ -136,7 +136,7 @@ body: | --- # CHECK-LABEL: name: test5 name: test5 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$ch', reg: '$bl' } diff --git a/llvm/test/CodeGen/X86/implicit-null-checks.mir b/llvm/test/CodeGen/X86/implicit-null-checks.mir index d7983553cc9..e6147f56ed7 100644 --- a/llvm/test/CodeGen/X86/implicit-null-checks.mir +++ b/llvm/test/CodeGen/X86/implicit-null-checks.mir @@ -384,7 +384,7 @@ --- name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -424,7 +424,7 @@ body: | ... --- name: imp_null_check_with_bitwise_op_1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -468,7 +468,7 @@ body: | --- name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -509,7 +509,7 @@ body: | --- name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -549,7 +549,7 @@ body: | --- name: imp_null_check_with_bitwise_op_4 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_4 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -590,7 +590,7 @@ body: | --- name: no_hoist_across_call # CHECK-LABEL: name: no_hoist_across_call -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -638,7 +638,7 @@ name: dependency_live_in_hazard # an implicit null check -- hoisting it will require hosting the move # to $esi and we cannot do that without clobbering the use of $rsi in # the first instruction in bb.1.not_null. -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -672,7 +672,7 @@ name: use_alternate_load_op # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -703,7 +703,7 @@ name: imp_null_check_gep_load_with_use_dep # CHECK: bb.0.entry: # CHECK: $eax = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $rdi, 1, $noreg, 0, $noreg, implicit-def $rax :: (load 4 from %ir.x) # CHECK-NEXT: JMP_1 %bb.1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -735,7 +735,7 @@ name: imp_null_check_load_with_base_sep # CHECK: $rsi = ADD64rr $rsi, $rdi, implicit-def dead $eflags # CHECK-NEXT: $esi = FAULTING_OP 1, %bb.2, {{[0-9]+}}, $esi, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags # CHECK-NEXT: JMP_1 %bb.1 -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -768,7 +768,7 @@ name: inc_store # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -798,7 +798,7 @@ name: inc_store_plus_offset # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -829,7 +829,7 @@ name: inc_store_with_dep # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -860,7 +860,7 @@ name: inc_store_with_dep_in_null # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -895,7 +895,7 @@ name: inc_store_with_volatile # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -925,7 +925,7 @@ name: inc_store_with_two_dep # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -957,7 +957,7 @@ name: inc_store_with_redefined_base # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -988,7 +988,7 @@ name: inc_store_with_reused_base # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1020,7 +1020,7 @@ name: inc_store_across_call # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1062,7 +1062,7 @@ name: inc_store_with_dep_in_dep # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1095,7 +1095,7 @@ name: inc_store_with_load_over_store # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1127,7 +1127,7 @@ name: inc_store_with_store_over_load # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1159,7 +1159,7 @@ name: inc_store_with_store_over_store # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1190,7 +1190,7 @@ name: inc_store_with_load_and_store # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1221,7 +1221,7 @@ name: inc_store_and_load_no_alias # CHECK-NEXT: JMP_1 %bb.1 # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1253,7 +1253,7 @@ name: inc_store_and_load_alias # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } @@ -1285,7 +1285,7 @@ name: inc_spill_dep # CHECK-NEXT: JCC_1 %bb.2, 4, implicit killed $eflags # CHECK: bb.1.not_null -alignment: 4 +alignment: 16 tracksRegLiveness: true stack: - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8} diff --git a/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir b/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir index 97f0064c475..6e83b207c2c 100644 --- a/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir +++ b/llvm/test/CodeGen/X86/implicit-null-chk-reg-rewrite.mir @@ -22,7 +22,7 @@ # that clobber the register used in TEST. name: reg-rewrite -alignment: 4 +alignment: 16 tracksRegLiveness: true liveins: - { reg: '$rdi' } diff --git a/llvm/test/CodeGen/X86/late-remat-update.mir b/llvm/test/CodeGen/X86/late-remat-update.mir index 31b6e7e71bc..a8fdc2ae5ac 100644 --- a/llvm/test/CodeGen/X86/late-remat-update.mir +++ b/llvm/test/CodeGen/X86/late-remat-update.mir @@ -54,7 +54,7 @@ ... --- name: _Z3fooi -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/lea-opt-with-debug.mir b/llvm/test/CodeGen/X86/lea-opt-with-debug.mir index a1cf2041db6..c2fcb7c9d6a 100644 --- a/llvm/test/CodeGen/X86/lea-opt-with-debug.mir +++ b/llvm/test/CodeGen/X86/lea-opt-with-debug.mir @@ -63,7 +63,7 @@ ... --- name: fn1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/leaFixup32.mir b/llvm/test/CodeGen/X86/leaFixup32.mir index 6d57cf2d977..f614a4ad975 100644 --- a/llvm/test/CodeGen/X86/leaFixup32.mir +++ b/llvm/test/CodeGen/X86/leaFixup32.mir @@ -78,7 +78,7 @@ ... --- name: test2add_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -113,7 +113,7 @@ body: | ... --- name: test2add_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -148,7 +148,7 @@ body: | ... --- name: test1add_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -182,7 +182,7 @@ body: | ... --- name: testleaadd_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -218,7 +218,7 @@ body: | ... --- name: testleaadd_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -254,7 +254,7 @@ body: | ... --- name: test1lea_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -289,7 +289,7 @@ body: | ... --- name: test2addi32_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -324,7 +324,7 @@ body: | ... --- name: test1mov1add_ebp_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -360,7 +360,7 @@ body: | ... --- name: testleaadd_ebp_index_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -395,7 +395,7 @@ body: | ... --- name: testleaadd_ebp_index2_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -430,7 +430,7 @@ body: | ... --- name: test_skip_opt_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -464,7 +464,7 @@ body: | ... --- name: test_skip_eflags_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/leaFixup64.mir b/llvm/test/CodeGen/X86/leaFixup64.mir index fa738adfd06..317c219992c 100644 --- a/llvm/test/CodeGen/X86/leaFixup64.mir +++ b/llvm/test/CodeGen/X86/leaFixup64.mir @@ -151,7 +151,7 @@ ... --- name: testleaadd_64_32_1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -186,7 +186,7 @@ body: | ... --- name: testleaadd_rbp_64_32_1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -221,7 +221,7 @@ body: | ... --- name: test1lea_rbp_64_32_1 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -255,7 +255,7 @@ body: | ... --- name: test2add_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -290,7 +290,7 @@ body: | ... --- name: test2add_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -325,7 +325,7 @@ body: | ... --- name: test1add_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -359,7 +359,7 @@ body: | ... --- name: testleaadd_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -395,7 +395,7 @@ body: | ... --- name: testleaadd_rbp_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -431,7 +431,7 @@ body: | ... --- name: test1lea_rbp_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -466,7 +466,7 @@ body: | ... --- name: testleaadd_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -502,7 +502,7 @@ body: | ... --- name: testleaadd_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -538,7 +538,7 @@ body: | ... --- name: test1lea_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -573,7 +573,7 @@ body: | ... --- name: test8 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -609,7 +609,7 @@ body: | ... --- name: testleaaddi32_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -644,7 +644,7 @@ body: | ... --- name: test1mov1add_rbp_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -678,7 +678,7 @@ body: | ... --- name: testleaadd_rbp_index_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -712,7 +712,7 @@ body: | ... --- name: testleaadd_rbp_index2_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -746,7 +746,7 @@ body: | ... --- name: test2addi32_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -781,7 +781,7 @@ body: | ... --- name: test1mov1add_rbp_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -816,7 +816,7 @@ body: | ... --- name: testleaadd_rbp_index_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -851,7 +851,7 @@ body: | ... --- name: testleaadd_rbp_index2_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -886,7 +886,7 @@ body: | ... --- name: test_skip_opt_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -920,7 +920,7 @@ body: | ... --- name: test_skip_eflags_64 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -962,7 +962,7 @@ body: | ... --- name: test_skip_opt_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false @@ -996,7 +996,7 @@ body: | ... --- name: test_skip_eflags_64_32 -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/limit-split-cost.mir b/llvm/test/CodeGen/X86/limit-split-cost.mir index 59c76661d0b..ac686826b4a 100644 --- a/llvm/test/CodeGen/X86/limit-split-cost.mir +++ b/llvm/test/CodeGen/X86/limit-split-cost.mir @@ -71,7 +71,7 @@ ... --- name: _Z3fooi -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/movtopush.mir b/llvm/test/CodeGen/X86/movtopush.mir index 98769a213bb..3d286bb498d 100644 --- a/llvm/test/CodeGen/X86/movtopush.mir +++ b/llvm/test/CodeGen/X86/movtopush.mir @@ -54,7 +54,7 @@ # CHECK-NEXT: ADJCALLSTACKUP32 20, 0, implicit-def dead $esp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $esp, implicit $ssp # CHECK-NEXT: RET 0 name: test9 -alignment: 0 +alignment: 1 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/non-value-mem-operand.mir b/llvm/test/CodeGen/X86/non-value-mem-operand.mir index 8e27cde9c11..8682d0657b2 100644 --- a/llvm/test/CodeGen/X86/non-value-mem-operand.mir +++ b/llvm/test/CodeGen/X86/non-value-mem-operand.mir @@ -120,7 +120,7 @@ ...
---
name: eggs
-alignment: 4
+alignment: 16
tracksRegLiveness: true
fixedStack:
- { id: 0, type: spill-slot, offset: -56, size: 8, alignment: 8, callee-saved-register: '$rbx' }
diff --git a/llvm/test/CodeGen/X86/opt_phis2.mir b/llvm/test/CodeGen/X86/opt_phis2.mir index 738a2da1f36..3683d31db17 100644 --- a/llvm/test/CodeGen/X86/opt_phis2.mir +++ b/llvm/test/CodeGen/X86/opt_phis2.mir @@ -9,7 +9,7 @@ ... --- name: test -alignment: 4 +alignment: 16 tracksRegLiveness: true jumpTable: kind: block-address diff --git a/llvm/test/CodeGen/X86/peephole-fold-testrr.mir b/llvm/test/CodeGen/X86/peephole-fold-testrr.mir index 1594f52cb0c..08e7c8bda04 100644 --- a/llvm/test/CodeGen/X86/peephole-fold-testrr.mir +++ b/llvm/test/CodeGen/X86/peephole-fold-testrr.mir @@ -22,7 +22,7 @@ ... --- name: atomic -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } @@ -55,7 +55,7 @@ body: | ... --- name: nonatomic_unoptimized -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir b/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir index 6487f4851aa..c0e5b508958 100644 --- a/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir +++ b/llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir @@ -65,7 +65,7 @@ # CHECK-NEXT: DBG_VALUE $eax, # CHECK: bb.2: name: x1 -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/X86/pr30821.mir b/llvm/test/CodeGen/X86/pr30821.mir index d134175652c..7ac7e3668e0 100644 --- a/llvm/test/CodeGen/X86/pr30821.mir +++ b/llvm/test/CodeGen/X86/pr30821.mir @@ -16,7 +16,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/pr38952.mir b/llvm/test/CodeGen/X86/pr38952.mir index 9a43dd2d8ce..ba2ffa8fefc 100644 --- a/llvm/test/CodeGen/X86/pr38952.mir +++ b/llvm/test/CodeGen/X86/pr38952.mir @@ -31,7 +31,7 @@ ... --- name: main -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/pre-coalesce.mir b/llvm/test/CodeGen/X86/pre-coalesce.mir index 8a783a79609..3051c009eb9 100644 --- a/llvm/test/CodeGen/X86/pre-coalesce.mir +++ b/llvm/test/CodeGen/X86/pre-coalesce.mir @@ -46,7 +46,7 @@ # CHECK: JCC_1 %[[L1]], 5 name: foo -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/regalloc-copy-hints.mir b/llvm/test/CodeGen/X86/regalloc-copy-hints.mir index 64a6a738084..591ba640206 100644 --- a/llvm/test/CodeGen/X86/regalloc-copy-hints.mir +++ b/llvm/test/CodeGen/X86/regalloc-copy-hints.mir @@ -15,7 +15,7 @@ # CHECK: hints: $ebx $edi # CHECK-NOT: hints: $ebx $edi $ebx $edi name: fun -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir b/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir index 33827e733b1..8bb10127f3c 100644 --- a/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir +++ b/llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir @@ -94,7 +94,7 @@ ... --- name: '@shrink_wrap_basic@16' -alignment: 4 +alignment: 16 exposesReturnsTwice: false legalized: false regBankSelected: false diff --git a/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir b/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir index 697e03d5c33..9536ba1dbc2 100644 --- a/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir +++ b/llvm/test/CodeGen/X86/sjlj-shadow-stack-liveness.mir @@ -11,7 +11,7 @@ --- name: bar # CHECK-LABEL: name: bar -alignment: 4 +alignment: 16 tracksRegLiveness: true body: | bb.0: diff --git a/llvm/test/CodeGen/X86/stack-folding-adx.mir b/llvm/test/CodeGen/X86/stack-folding-adx.mir index ec74eeb3a34..99e24cb12d1 100644 --- a/llvm/test/CodeGen/X86/stack-folding-adx.mir +++ b/llvm/test/CodeGen/X86/stack-folding-adx.mir @@ -61,7 +61,7 @@ ... --- name: stack_fold_adcx32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -113,7 +113,7 @@ body: | ... --- name: stack_fold_adcx64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -165,7 +165,7 @@ body: | ... --- name: stack_fold_adox32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -217,7 +217,7 @@ body: | ... --- name: stack_fold_adox64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } diff --git a/llvm/test/CodeGen/X86/stack-folding-bmi2.mir b/llvm/test/CodeGen/X86/stack-folding-bmi2.mir index ab97872e443..604f7bdacdf 100644 --- a/llvm/test/CodeGen/X86/stack-folding-bmi2.mir +++ b/llvm/test/CodeGen/X86/stack-folding-bmi2.mir @@ -33,7 +33,7 @@ ... --- name: stack_fold_mulx_u32 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -68,7 +68,7 @@ body: | ... --- name: stack_fold_mulx_u64 -alignment: 4 +alignment: 16 tracksRegLiveness: true registers: - { id: 0, class: gr64 } diff --git a/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir b/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir index b7755ba5d52..d95bfc0810d 100644 --- a/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir +++ b/llvm/test/CodeGen/X86/win_coreclr_chkstk_liveins.mir @@ -4,7 +4,7 @@ name: main4k # CHECK-LABEL: name: main4k -alignment: 4 +alignment: 16 tracksRegLiveness: true frameInfo: maxAlignment: 8 |
