diff options
Diffstat (limited to 'llvm/test/CodeGen/AArch64')
17 files changed, 1335 insertions, 1318 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir index fe22db27087..a99104f9cbc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s # Check the default mappings for various instructions. @@ -72,458 +73,454 @@ ... --- -# CHECK-LABEL: name: test_add_s32 name: test_add_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_ADD %0, %0 + ; CHECK-LABEL: name: test_add_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[ADD:%[0-9]+]](s32) = G_ADD [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_ADD %0, %0 ... --- -# CHECK-LABEL: name: test_add_v4s32 name: test_add_v4s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_ADD %0, %0 + ; CHECK-LABEL: name: test_add_v4s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0 + ; CHECK: [[ADD:%[0-9]+]](<4 x s32>) = G_ADD [[COPY]], [[COPY]] %0(<4 x s32>) = COPY %q0 %1(<4 x s32>) = G_ADD %0, %0 ... --- -# CHECK-LABEL: name: test_sub_s32 name: test_sub_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_SUB %0, %0 + ; CHECK-LABEL: name: test_sub_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[SUB:%[0-9]+]](s32) = G_SUB [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_SUB %0, %0 ... --- -# CHECK-LABEL: name: test_sub_v4s32 name: test_sub_v4s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_SUB %0, %0 + ; CHECK-LABEL: name: test_sub_v4s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0 + ; CHECK: [[SUB:%[0-9]+]](<4 x s32>) = G_SUB [[COPY]], [[COPY]] %0(<4 x s32>) = COPY %q0 %1(<4 x s32>) = G_SUB %0, %0 ... --- -# CHECK-LABEL: name: test_mul_s32 name: test_mul_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_MUL %0, %0 + ; CHECK-LABEL: name: test_mul_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[MUL:%[0-9]+]](s32) = G_MUL [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_MUL %0, %0 ... --- -# CHECK-LABEL: name: test_mul_v4s32 name: test_mul_v4s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_MUL %0, %0 + ; CHECK-LABEL: name: test_mul_v4s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0 + ; CHECK: [[MUL:%[0-9]+]](<4 x s32>) = G_MUL [[COPY]], [[COPY]] %0(<4 x s32>) = COPY %q0 %1(<4 x s32>) = G_MUL %0, %0 ... --- -# CHECK-LABEL: name: test_and_s32 name: test_and_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_AND %0, %0 + ; CHECK-LABEL: name: test_and_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[AND:%[0-9]+]](s32) = G_AND [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_AND %0, %0 ... --- -# CHECK-LABEL: name: test_and_v4s32 name: test_and_v4s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_AND %0, %0 + ; CHECK-LABEL: name: test_and_v4s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0 + ; CHECK: [[AND:%[0-9]+]](<4 x s32>) = G_AND [[COPY]], [[COPY]] %0(<4 x s32>) = COPY %q0 %1(<4 x s32>) = G_AND %0, %0 ... --- -# CHECK-LABEL: name: test_or_s32 name: test_or_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_OR %0, %0 + ; CHECK-LABEL: name: test_or_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[OR:%[0-9]+]](s32) = G_OR [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_OR %0, %0 ... --- -# CHECK-LABEL: name: test_or_v4s32 name: test_or_v4s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_OR %0, %0 + ; CHECK-LABEL: name: test_or_v4s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0 + ; CHECK: [[OR:%[0-9]+]](<4 x s32>) = G_OR [[COPY]], [[COPY]] %0(<4 x s32>) = COPY %q0 %1(<4 x s32>) = G_OR %0, %0 ... --- -# CHECK-LABEL: name: test_xor_s32 name: test_xor_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_XOR %0, %0 + ; CHECK-LABEL: name: test_xor_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[XOR:%[0-9]+]](s32) = G_XOR [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_XOR %0, %0 ... --- -# CHECK-LABEL: name: test_xor_v4s32 name: test_xor_v4s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_XOR %0, %0 + ; CHECK-LABEL: name: test_xor_v4s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0 + ; CHECK: [[XOR:%[0-9]+]](<4 x s32>) = G_XOR [[COPY]], [[COPY]] %0(<4 x s32>) = COPY %q0 %1(<4 x s32>) = G_XOR %0, %0 ... --- -# CHECK-LABEL: name: test_shl_s32 name: test_shl_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_SHL %0, %0 + ; CHECK-LABEL: name: test_shl_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[SHL:%[0-9]+]](s32) = G_SHL [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_SHL %0, %0 ... --- -# CHECK-LABEL: name: test_shl_v4s32 name: test_shl_v4s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %q0 - ; CHECK: %0(<4 x s32>) = COPY %q0 - ; CHECK: %1(<4 x s32>) = G_SHL %0, %0 + ; CHECK-LABEL: name: test_shl_v4s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](<4 x s32>) = COPY %q0 + ; CHECK: [[SHL:%[0-9]+]](<4 x s32>) = G_SHL [[COPY]], [[COPY]] %0(<4 x s32>) = COPY %q0 %1(<4 x s32>) = G_SHL %0, %0 ... --- -# CHECK-LABEL: name: test_lshr_s32 name: test_lshr_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_LSHR %0, %0 + ; CHECK-LABEL: name: test_lshr_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[LSHR:%[0-9]+]](s32) = G_LSHR [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_LSHR %0, %0 ... --- -# CHECK-LABEL: name: test_ashr_s32 name: test_ashr_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_ASHR %0, %0 + ; CHECK-LABEL: name: test_ashr_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[ASHR:%[0-9]+]](s32) = G_ASHR [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_ASHR %0, %0 ... --- -# CHECK-LABEL: name: test_sdiv_s32 name: test_sdiv_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_SDIV %0, %0 + ; CHECK-LABEL: name: test_sdiv_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[SDIV:%[0-9]+]](s32) = G_SDIV [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_SDIV %0, %0 ... --- -# CHECK-LABEL: name: test_udiv_s32 name: test_udiv_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_UDIV %0, %0 + ; CHECK-LABEL: name: test_udiv_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[UDIV:%[0-9]+]](s32) = G_UDIV [[COPY]], [[COPY]] %0(s32) = COPY %w0 %1(s32) = G_UDIV %0, %0 ... --- -# CHECK-LABEL: name: test_anyext_s64_s32 name: test_anyext_s64_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_ANYEXT %0 + ; CHECK-LABEL: name: test_anyext_s64_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[ANYEXT:%[0-9]+]](s64) = G_ANYEXT [[COPY]](s32) %0(s32) = COPY %w0 %1(s64) = G_ANYEXT %0 ... --- -# CHECK-LABEL: name: test_sext_s64_s32 name: test_sext_s64_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_SEXT %0 + ; CHECK-LABEL: name: test_sext_s64_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[SEXT:%[0-9]+]](s64) = G_SEXT [[COPY]](s32) %0(s32) = COPY %w0 %1(s64) = G_SEXT %0 ... --- -# CHECK-LABEL: name: test_zext_s64_s32 name: test_zext_s64_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_ZEXT %0 + ; CHECK-LABEL: name: test_zext_s64_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[ZEXT:%[0-9]+]](s64) = G_ZEXT [[COPY]](s32) %0(s32) = COPY %w0 %1(s64) = G_ZEXT %0 ... --- -# CHECK-LABEL: name: test_trunc_s32_s64 name: test_trunc_s32_s64 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %x0 - ; CHECK: %0(s64) = COPY %x0 - ; CHECK: %1(s32) = G_TRUNC %0 + ; CHECK-LABEL: name: test_trunc_s32_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0 + ; CHECK: [[TRUNC:%[0-9]+]](s32) = G_TRUNC [[COPY]](s64) %0(s64) = COPY %x0 %1(s32) = G_TRUNC %0 ... --- -# CHECK-LABEL: name: test_constant_s32 name: test_constant_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } body: | bb.0: - ; CHECK: %0(s32) = G_CONSTANT 123 + ; CHECK-LABEL: name: test_constant_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK: [[C:%[0-9]+]](s32) = G_CONSTANT 123 %0(s32) = G_CONSTANT 123 ... --- -# CHECK-LABEL: name: test_constant_p0 name: test_constant_p0 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } body: | bb.0: - ; CHECK: %0(p0) = G_CONSTANT 0 + ; CHECK-LABEL: name: test_constant_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK: [[C:%[0-9]+]](p0) = G_CONSTANT 0 %0(p0) = G_CONSTANT 0 ... --- -# CHECK-LABEL: name: test_icmp_s32 name: test_icmp_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -531,21 +528,22 @@ registers: body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s32) = G_ICMP intpred(ne), %0(s32), %0 - ; CHECK: %2(s1) = G_TRUNC %1(s32) + ; CHECK-LABEL: name: test_icmp_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY]] + ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[ICMP]](s32) %0(s32) = COPY %w0 %1(s32) = G_ICMP intpred(ne), %0, %0 %2(s1) = G_TRUNC %1(s32) ... --- -# CHECK-LABEL: name: test_icmp_p0 name: test_icmp_p0 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -553,243 +551,244 @@ registers: body: | bb.0: liveins: %x0 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s32) = G_ICMP intpred(ne), %0(p0), %0 - ; CHECK: %2(s1) = G_TRUNC %1(s32) + ; CHECK-LABEL: name: test_icmp_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0 + ; CHECK: [[ICMP:%[0-9]+]](s32) = G_ICMP intpred(ne), [[COPY]](p0), [[COPY]] + ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[ICMP]](s32) %0(p0) = COPY %x0 %1(s32) = G_ICMP intpred(ne), %0, %0 %2(s1) = G_TRUNC %1(s32) ... --- -# CHECK-LABEL: name: test_frame_index_p0 name: test_frame_index_p0 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } stack: - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } body: | bb.0: - ; CHECK: %0(p0) = G_FRAME_INDEX %stack.0.ptr0 + ; CHECK-LABEL: name: test_frame_index_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK: [[FRAME_INDEX:%[0-9]+]](p0) = G_FRAME_INDEX %stack.0.ptr0 %0(p0) = G_FRAME_INDEX %stack.0.ptr0 ... --- -# CHECK-LABEL: name: test_ptrtoint_s64_p0 name: test_ptrtoint_s64_p0 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %x0 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s64) = G_PTRTOINT %0 + ; CHECK-LABEL: name: test_ptrtoint_s64_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0 + ; CHECK: [[PTRTOINT:%[0-9]+]](s64) = G_PTRTOINT [[COPY]](p0) %0(p0) = COPY %x0 %1(s64) = G_PTRTOINT %0 ... --- -# CHECK-LABEL: name: test_inttoptr_p0_s64 name: test_inttoptr_p0_s64 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %x0 - ; CHECK: %0(s64) = COPY %x0 - ; CHECK: %1(p0) = G_INTTOPTR %0 + ; CHECK-LABEL: name: test_inttoptr_p0_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0 + ; CHECK: [[INTTOPTR:%[0-9]+]](p0) = G_INTTOPTR [[COPY]](s64) %0(s64) = COPY %x0 %1(p0) = G_INTTOPTR %0 ... --- -# CHECK-LABEL: name: test_load_s32_p0 name: test_load_s32_p0 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %x0 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s32) = G_LOAD %0 + ; CHECK-LABEL: name: test_load_s32_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0 + ; CHECK: [[LOAD:%[0-9]+]](s32) = G_LOAD [[COPY]](p0) :: (load 4) %0(p0) = COPY %x0 %1(s32) = G_LOAD %0 :: (load 4) ... --- -# CHECK-LABEL: name: test_store_s32_p0 name: test_store_s32_p0 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %x0, %w1 - ; CHECK: %0(p0) = COPY %x0 - ; CHECK: %1(s32) = COPY %w1 - ; CHECK: G_STORE %1(s32), %0(p0) + ; CHECK-LABEL: name: test_store_s32_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]](s32) = COPY %w1 + ; CHECK: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store 4) %0(p0) = COPY %x0 %1(s32) = COPY %w1 G_STORE %1, %0 :: (store 4) ... --- -# CHECK-LABEL: name: test_fadd_s32 name: test_fadd_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FADD %0, %0 + ; CHECK-LABEL: name: test_fadd_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0 + ; CHECK: [[FADD:%[0-9]+]](s32) = G_FADD [[COPY]], [[COPY]] %0(s32) = COPY %s0 %1(s32) = G_FADD %0, %0 ... --- -# CHECK-LABEL: name: test_fsub_s32 name: test_fsub_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FSUB %0, %0 + ; CHECK-LABEL: name: test_fsub_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0 + ; CHECK: [[FSUB:%[0-9]+]](s32) = G_FSUB [[COPY]], [[COPY]] %0(s32) = COPY %s0 %1(s32) = G_FSUB %0, %0 ... --- -# CHECK-LABEL: name: test_fmul_s32 name: test_fmul_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FMUL %0, %0 + ; CHECK-LABEL: name: test_fmul_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0 + ; CHECK: [[FMUL:%[0-9]+]](s32) = G_FMUL [[COPY]], [[COPY]] %0(s32) = COPY %s0 %1(s32) = G_FMUL %0, %0 ... --- -# CHECK-LABEL: name: test_fdiv_s32 name: test_fdiv_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s32) = G_FDIV %0, %0 + ; CHECK-LABEL: name: test_fdiv_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0 + ; CHECK: [[FDIV:%[0-9]+]](s32) = G_FDIV [[COPY]], [[COPY]] %0(s32) = COPY %s0 %1(s32) = G_FDIV %0, %0 ... --- -# CHECK-LABEL: name: test_fpext_s64_s32 name: test_fpext_s64_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s64) = G_FPEXT %0 + ; CHECK-LABEL: name: test_fpext_s64_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0 + ; CHECK: [[FPEXT:%[0-9]+]](s64) = G_FPEXT [[COPY]](s32) %0(s32) = COPY %s0 %1(s64) = G_FPEXT %0 ... --- -# CHECK-LABEL: name: test_fptrunc_s32_s64 name: test_fptrunc_s32_s64 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %d0 - ; CHECK: %0(s64) = COPY %d0 - ; CHECK: %1(s32) = G_FPTRUNC %0 + ; CHECK-LABEL: name: test_fptrunc_s32_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %d0 + ; CHECK: [[FPTRUNC:%[0-9]+]](s32) = G_FPTRUNC [[COPY]](s64) %0(s64) = COPY %d0 %1(s32) = G_FPTRUNC %0 ... --- -# CHECK-LABEL: name: test_fconstant_s32 name: test_fconstant_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } body: | bb.0: - ; CHECK: %0(s32) = G_FCONSTANT float 1.0 + ; CHECK-LABEL: name: test_fconstant_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK: [[C:%[0-9]+]](s32) = G_FCONSTANT float 1.000000e+00 %0(s32) = G_FCONSTANT float 1.0 ... --- -# CHECK-LABEL: name: test_fcmp_s32 name: test_fcmp_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } @@ -797,100 +796,99 @@ registers: body: | bb.0: liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: [[FCMP:%[0-9]+]](s32) = G_FCMP floatpred(olt), %0(s32), %0 - ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FCMP]] + ; CHECK-LABEL: name: test_fcmp_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0 + ; CHECK: [[FCMP:%[0-9]+]](s32) = G_FCMP floatpred(olt), [[COPY]](s32), [[COPY]] + ; CHECK: [[TRUNC:%[0-9]+]](s1) = G_TRUNC [[FCMP]](s32) %0(s32) = COPY %s0 %1(s32) = G_FCMP floatpred(olt), %0, %0 %2(s1) = G_TRUNC %1(s32) ... --- -# CHECK-LABEL: name: test_sitofp_s64_s32 name: test_sitofp_s64_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %w0 - ; CHECK: %0(s32) = COPY %w0 - ; CHECK: %1(s64) = G_SITOFP %0 + ; CHECK-LABEL: name: test_sitofp_s64_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[SITOFP:%[0-9]+]](s64) = G_SITOFP [[COPY]](s32) %0(s32) = COPY %w0 %1(s64) = G_SITOFP %0 ... --- -# CHECK-LABEL: name: test_uitofp_s32_s64 name: test_uitofp_s32_s64 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: fpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %x0 - ; CHECK: %0(s64) = COPY %x0 - ; CHECK: %1(s32) = G_UITOFP %0 + ; CHECK-LABEL: name: test_uitofp_s32_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: fpr + ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %x0 + ; CHECK: [[UITOFP:%[0-9]+]](s32) = G_UITOFP [[COPY]](s64) %0(s64) = COPY %x0 %1(s32) = G_UITOFP %0 ... --- -# CHECK-LABEL: name: test_fptosi_s64_s32 name: test_fptosi_s64_s32 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %s0 - ; CHECK: %0(s32) = COPY %s0 - ; CHECK: %1(s64) = G_FPTOSI %0 + ; CHECK-LABEL: name: test_fptosi_s64_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s32) = COPY %s0 + ; CHECK: [[FPTOSI:%[0-9]+]](s64) = G_FPTOSI [[COPY]](s32) %0(s32) = COPY %s0 %1(s64) = G_FPTOSI %0 ... --- -# CHECK-LABEL: name: test_fptoui_s32_s64 name: test_fptoui_s32_s64 legalized: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: _ } - { id: 1, class: _ } body: | bb.0: liveins: %d0 - ; CHECK: %0(s64) = COPY %d0 - ; CHECK: %1(s32) = G_FPTOUI %0 + ; CHECK-LABEL: name: test_fptoui_s32_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]](s64) = COPY %d0 + ; CHECK: [[FPTOUI:%[0-9]+]](s32) = G_FPTOUI [[COPY]](s64) %0(s64) = COPY %d0 %1(s32) = G_FPTOUI %0 ... --- -# CHECK-LABEL: name: test_gphi_ptr name: test_gphi_ptr legalized: true tracksRegLiveness: true -# CHECK: registers: -# CHECK: - { id: 0, class: gpr, preferred-register: '' } -# CHECK: - { id: 1, class: gpr, preferred-register: '' } -# CHECK: - { id: 2, class: gpr, preferred-register: '' } -# CHECK: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: _, preferred-register: '' } - { id: 1, class: _, preferred-register: '' } @@ -899,6 +897,28 @@ registers: - { id: 4, class: _, preferred-register: '' } - { id: 5, class: _, preferred-register: '' } body: | + ; CHECK-LABEL: name: test_gphi_ptr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK-NEXT: id: 4, class: _ + ; CHECK-NEXT: id: 5, class: _ + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000) + ; CHECK: liveins: %w2, %x0, %x1 + ; CHECK: [[COPY:%[0-9]+]](p0) = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]](p0) = COPY %x1 + ; CHECK: [[COPY2:%[0-9]+]](s1) = COPY %w2 + ; CHECK: G_BRCOND [[COPY2]](s1), %bb.1 + ; CHECK: G_BR %bb.2 + ; CHECK: bb.1: + ; CHECK: successors: %bb.2(0x80000000) + ; CHECK: bb.2: + ; CHECK: [[PHI:%[0-9]+]](p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1 + ; CHECK: %x0 = COPY [[PHI]](p0) + ; CHECK: RET_ReallyLR implicit %x0 bb.0: successors: %bb.1, %bb.2 liveins: %w2, %x0, %x1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir index 70cda516d5f..78d34bf5655 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-binop.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -58,28 +59,28 @@ --- # Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32. # Also check that we constrain the register class of the COPY to GPR32. -# CHECK-LABEL: name: add_s32_gpr name: add_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ADDWrr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: add_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[ADDWrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ADD %0, %1 @@ -88,28 +89,28 @@ body: | --- # Same as add_s32_gpr, for 64-bit operations. -# CHECK-LABEL: name: add_s64_gpr name: add_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ADDXrr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: add_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[ADDXrr:%[0-9]+]] = ADDXrr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[ADDXrr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_ADD %0, %1 @@ -117,27 +118,27 @@ body: | ... --- -# CHECK-LABEL: name: add_imm_s32_gpr name: add_imm_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32sp, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = ADDWri %0, 1, 0 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: add_imm_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr32sp + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[ADDWri:%[0-9]+]] = ADDWri [[COPY]], 1, 0 + ; CHECK: %w0 = COPY [[ADDWri]] %0(s32) = COPY %w0 %1(s32) = G_CONSTANT i32 1 %2(s32) = G_ADD %0, %1 @@ -145,27 +146,27 @@ body: | ... --- -# CHECK-LABEL: name: add_imm_s64_gpr name: add_imm_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64sp, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %2 = ADDXri %0, 1, 0 body: | bb.0: liveins: %x0, %w1 + ; CHECK-LABEL: name: add_imm_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr64sp + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[ADDXri:%[0-9]+]] = ADDXri [[COPY]], 1, 0 + ; CHECK: %x0 = COPY [[ADDXri]] %0(s64) = COPY %x0 %1(s64) = G_CONSTANT i32 1 %2(s64) = G_ADD %0, %1 @@ -173,25 +174,28 @@ body: | ... --- -# CHECK-LABEL: name: add_imm_s32_gpr_bb name: add_imm_s32_gpr_bb legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32sp, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: bb.1: -# CHECK: %2 = ADDWri %0, 1, 0 body: | + ; CHECK-LABEL: name: add_imm_s32_gpr_bb + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr32sp + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: B %bb.1 + ; CHECK: bb.1: + ; CHECK: [[ADDWri:%[0-9]+]] = ADDWri [[COPY]], 1, 0 + ; CHECK: %w0 = COPY [[ADDWri]] bb.0: liveins: %w0, %w1 successors: %bb.1 @@ -207,28 +211,28 @@ body: | --- # Same as add_s32_gpr, for G_SUB operations. -# CHECK-LABEL: name: sub_s32_gpr name: sub_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = SUBSWrr %0, %1, implicit-def %nzcv body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: sub_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[SUBSWrr:%[0-9]+]] = SUBSWrr [[COPY]], [[COPY1]], implicit-def %nzcv + ; CHECK: %w0 = COPY [[SUBSWrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_SUB %0, %1 @@ -237,28 +241,28 @@ body: | --- # Same as add_s64_gpr, for G_SUB operations. -# CHECK-LABEL: name: sub_s64_gpr name: sub_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = SUBSXrr %0, %1, implicit-def %nzcv body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: sub_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[SUBSXrr:%[0-9]+]] = SUBSXrr [[COPY]], [[COPY1]], implicit-def %nzcv + ; CHECK: %x0 = COPY [[SUBSXrr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_SUB %0, %1 @@ -267,28 +271,28 @@ body: | --- # Same as add_s32_gpr, for G_OR operations. -# CHECK-LABEL: name: or_s32_gpr name: or_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ORRWrr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: or_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[ORRWrr:%[0-9]+]] = ORRWrr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[ORRWrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_OR %0, %1 @@ -297,28 +301,28 @@ body: | --- # Same as add_s64_gpr, for G_OR operations. -# CHECK-LABEL: name: or_s64_gpr name: or_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ORRXrr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: or_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[ORRXrr:%[0-9]+]] = ORRXrr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[ORRXrr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_OR %0, %1 @@ -327,30 +331,30 @@ body: | --- # 64-bit G_OR on vector registers. -# CHECK-LABEL: name: or_v2s32_fpr name: or_v2s32_fpr legalized: true regBankSelected: true # -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 # The actual OR does not matter as long as it is operating # on 64-bit width vector. -# CHECK: %2 = ORRv8i8 %0, %1 body: | bb.0: liveins: %d0, %d1 + ; CHECK-LABEL: name: or_v2s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK-NEXT: id: 2, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1 + ; CHECK: [[ORRv8i8_:%[0-9]+]] = ORRv8i8 [[COPY]], [[COPY1]] + ; CHECK: %d0 = COPY [[ORRv8i8_]] %0(<2 x s32>) = COPY %d0 %1(<2 x s32>) = COPY %d1 %2(<2 x s32>) = G_OR %0, %1 @@ -359,28 +363,28 @@ body: | --- # Same as add_s32_gpr, for G_AND operations. -# CHECK-LABEL: name: and_s32_gpr name: and_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ANDWrr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: and_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[ANDWrr:%[0-9]+]] = ANDWrr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[ANDWrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_AND %0, %1 @@ -389,28 +393,28 @@ body: | --- # Same as add_s64_gpr, for G_AND operations. -# CHECK-LABEL: name: and_s64_gpr name: and_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ANDXrr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: and_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[ANDXrr:%[0-9]+]] = ANDXrr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[ANDXrr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_AND %0, %1 @@ -419,28 +423,28 @@ body: | --- # Same as add_s32_gpr, for G_SHL operations. -# CHECK-LABEL: name: shl_s32_gpr name: shl_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = LSLVWr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: shl_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[LSLVWr:%[0-9]+]] = LSLVWr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[LSLVWr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_SHL %0, %1 @@ -449,28 +453,28 @@ body: | --- # Same as add_s64_gpr, for G_SHL operations. -# CHECK-LABEL: name: shl_s64_gpr name: shl_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = LSLVXr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: shl_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[LSLVXr:%[0-9]+]] = LSLVXr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[LSLVXr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_SHL %0, %1 @@ -479,28 +483,28 @@ body: | --- # Same as add_s32_gpr, for G_LSHR operations. -# CHECK-LABEL: name: lshr_s32_gpr name: lshr_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = LSRVWr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: lshr_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[LSRVWr:%[0-9]+]] = LSRVWr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[LSRVWr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_LSHR %0, %1 @@ -509,28 +513,28 @@ body: | --- # Same as add_s64_gpr, for G_LSHR operations. -# CHECK-LABEL: name: lshr_s64_gpr name: lshr_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = LSRVXr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: lshr_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[LSRVXr:%[0-9]+]] = LSRVXr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[LSRVXr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_LSHR %0, %1 @@ -539,28 +543,28 @@ body: | --- # Same as add_s32_gpr, for G_ASHR operations. -# CHECK-LABEL: name: ashr_s32_gpr name: ashr_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = ASRVWr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: ashr_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[ASRVWr:%[0-9]+]] = ASRVWr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[ASRVWr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_ASHR %0, %1 @@ -569,28 +573,28 @@ body: | --- # Same as add_s64_gpr, for G_ASHR operations. -# CHECK-LABEL: name: ashr_s64_gpr name: ashr_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = ASRVXr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: ashr_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[ASRVXr:%[0-9]+]] = ASRVXr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[ASRVXr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_ASHR %0, %1 @@ -600,28 +604,28 @@ body: | --- # Check that we select s32 GPR G_MUL. This is trickier than other binops because # there is only MADDWrrr, and we have to use the WZR physreg. -# CHECK-LABEL: name: mul_s32_gpr name: mul_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = MADDWrrr %0, %1, %wzr body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: mul_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[MADDWrrr:%[0-9]+]] = MADDWrrr [[COPY]], [[COPY1]], %wzr + ; CHECK: %w0 = COPY [[MADDWrrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_MUL %0, %1 @@ -630,28 +634,28 @@ body: | --- # Same as mul_s32_gpr for the s64 type. -# CHECK-LABEL: name: mul_s64_gpr name: mul_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = MADDXrrr %0, %1, %xzr body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: mul_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[MADDXrrr:%[0-9]+]] = MADDXrrr [[COPY]], [[COPY1]], %xzr + ; CHECK: %x0 = COPY [[MADDXrrr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_MUL %0, %1 @@ -660,26 +664,27 @@ body: | --- # Same as mul_s32_gpr for the s64 type. -# CHECK-LABEL: name: mulh_s64_gpr name: mulh_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr64, preferred-register: '' } - -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = SMULHrr %0, %1 -# CHECK: %3 = UMULHrr %0, %1 + body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: mulh_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK-NEXT: id: 3, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[SMULHrr:%[0-9]+]] = SMULHrr [[COPY]], [[COPY1]] + ; CHECK: [[UMULHrr:%[0-9]+]] = UMULHrr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[SMULHrr]] + ; CHECK: %x0 = COPY [[UMULHrr]] %0:gpr(s64) = COPY %x0 %1:gpr(s64) = COPY %x1 %2:gpr(s64) = G_SMULH %0, %1 @@ -690,28 +695,28 @@ body: | --- # Same as add_s32_gpr, for G_SDIV operations. -# CHECK-LABEL: name: sdiv_s32_gpr name: sdiv_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = SDIVWr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: sdiv_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[SDIVWr:%[0-9]+]] = SDIVWr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[SDIVWr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_SDIV %0, %1 @@ -720,28 +725,28 @@ body: | --- # Same as add_s64_gpr, for G_SDIV operations. -# CHECK-LABEL: name: sdiv_s64_gpr name: sdiv_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = SDIVXr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: sdiv_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[SDIVXr:%[0-9]+]] = SDIVXr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[SDIVXr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_SDIV %0, %1 @@ -750,28 +755,28 @@ body: | --- # Same as add_s32_gpr, for G_UDIV operations. -# CHECK-LABEL: name: udiv_s32_gpr name: udiv_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = UDIVWr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: udiv_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[UDIVWr:%[0-9]+]] = UDIVWr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[UDIVWr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_UDIV %0, %1 @@ -780,28 +785,28 @@ body: | --- # Same as add_s64_gpr, for G_UDIV operations. -# CHECK-LABEL: name: udiv_s64_gpr name: udiv_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = UDIVXr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: udiv_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[UDIVXr:%[0-9]+]] = UDIVXr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[UDIVXr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_UDIV %0, %1 @@ -810,28 +815,28 @@ body: | --- # Check that we select a s32 FPR G_FADD into FADDSrr. -# CHECK-LABEL: name: fadd_s32_fpr name: fadd_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FADDSrr %0, %1 body: | bb.0: liveins: %s0, %s1 + ; CHECK-LABEL: name: fadd_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK-NEXT: id: 2, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1 + ; CHECK: [[FADDSrr:%[0-9]+]] = FADDSrr [[COPY]], [[COPY1]] + ; CHECK: %s0 = COPY [[FADDSrr]] %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s32) = G_FADD %0, %1 @@ -839,28 +844,28 @@ body: | ... --- -# CHECK-LABEL: name: fadd_s64_fpr name: fadd_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FADDDrr %0, %1 body: | bb.0: liveins: %d0, %d1 + ; CHECK-LABEL: name: fadd_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK-NEXT: id: 2, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1 + ; CHECK: [[FADDDrr:%[0-9]+]] = FADDDrr [[COPY]], [[COPY1]] + ; CHECK: %d0 = COPY [[FADDDrr]] %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s64) = G_FADD %0, %1 @@ -868,28 +873,28 @@ body: | ... --- -# CHECK-LABEL: name: fsub_s32_fpr name: fsub_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FSUBSrr %0, %1 body: | bb.0: liveins: %s0, %s1 + ; CHECK-LABEL: name: fsub_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK-NEXT: id: 2, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1 + ; CHECK: [[FSUBSrr:%[0-9]+]] = FSUBSrr [[COPY]], [[COPY1]] + ; CHECK: %s0 = COPY [[FSUBSrr]] %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s32) = G_FSUB %0, %1 @@ -897,28 +902,28 @@ body: | ... --- -# CHECK-LABEL: name: fsub_s64_fpr name: fsub_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FSUBDrr %0, %1 body: | bb.0: liveins: %d0, %d1 + ; CHECK-LABEL: name: fsub_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK-NEXT: id: 2, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1 + ; CHECK: [[FSUBDrr:%[0-9]+]] = FSUBDrr [[COPY]], [[COPY1]] + ; CHECK: %d0 = COPY [[FSUBDrr]] %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s64) = G_FSUB %0, %1 @@ -926,28 +931,28 @@ body: | ... --- -# CHECK-LABEL: name: fmul_s32_fpr name: fmul_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FMULSrr %0, %1 body: | bb.0: liveins: %s0, %s1 + ; CHECK-LABEL: name: fmul_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK-NEXT: id: 2, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1 + ; CHECK: [[FMULSrr:%[0-9]+]] = FMULSrr [[COPY]], [[COPY1]] + ; CHECK: %s0 = COPY [[FMULSrr]] %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s32) = G_FMUL %0, %1 @@ -955,28 +960,28 @@ body: | ... --- -# CHECK-LABEL: name: fmul_s64_fpr name: fmul_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FMULDrr %0, %1 body: | bb.0: liveins: %d0, %d1 + ; CHECK-LABEL: name: fmul_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK-NEXT: id: 2, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1 + ; CHECK: [[FMULDrr:%[0-9]+]] = FMULDrr [[COPY]], [[COPY1]] + ; CHECK: %d0 = COPY [[FMULDrr]] %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s64) = G_FMUL %0, %1 @@ -984,28 +989,28 @@ body: | ... --- -# CHECK-LABEL: name: fdiv_s32_fpr name: fdiv_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %s1 -# CHECK: %2 = FDIVSrr %0, %1 body: | bb.0: liveins: %s0, %s1 + ; CHECK-LABEL: name: fdiv_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK-NEXT: id: 2, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1 + ; CHECK: [[FDIVSrr:%[0-9]+]] = FDIVSrr [[COPY]], [[COPY1]] + ; CHECK: %s0 = COPY [[FDIVSrr]] %0(s32) = COPY %s0 %1(s32) = COPY %s1 %2(s32) = G_FDIV %0, %1 @@ -1013,28 +1018,28 @@ body: | ... --- -# CHECK-LABEL: name: fdiv_s64_fpr name: fdiv_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %d1 -# CHECK: %2 = FDIVDrr %0, %1 body: | bb.0: liveins: %d0, %d1 + ; CHECK-LABEL: name: fdiv_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK-NEXT: id: 2, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1 + ; CHECK: [[FDIVDrr:%[0-9]+]] = FDIVDrr [[COPY]], [[COPY1]] + ; CHECK: %d0 = COPY [[FDIVDrr]] %0(s64) = COPY %d0 %1(s64) = COPY %d1 %2(s64) = G_FDIV %0, %1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir index fe077a25f7c..c19d0d4b187 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -16,248 +17,248 @@ ... --- -# CHECK-LABEL: name: bitcast_s32_gpr name: bitcast_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: bitcast_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32all + ; CHECK-NEXT: id: 1, class: gpr32all + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %w0 = COPY [[COPY1]] %0(s32) = COPY %w0 %1(s32) = G_BITCAST %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: bitcast_s32_fpr name: bitcast_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %s0 + ; CHECK-LABEL: name: bitcast_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %s0 = COPY [[COPY1]] %0(s32) = COPY %s0 %1(s32) = G_BITCAST %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: bitcast_s32_gpr_fpr name: bitcast_s32_gpr_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: bitcast_s32_gpr_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32all + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %s0 = COPY [[COPY1]] %0(s32) = COPY %w0 %1(s32) = G_BITCAST %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: bitcast_s32_fpr_gpr name: bitcast_s32_fpr_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %s0 + ; CHECK-LABEL: name: bitcast_s32_fpr_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %w0 = COPY [[COPY1]] %0(s32) = COPY %s0 %1(s32) = G_BITCAST %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: bitcast_s64_gpr name: bitcast_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: bitcast_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64all + ; CHECK-NEXT: id: 1, class: gpr64all + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %x0 = COPY [[COPY1]] %0(s64) = COPY %x0 %1(s64) = G_BITCAST %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: bitcast_s64_fpr name: bitcast_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: bitcast_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %d0 = COPY [[COPY1]] %0(s64) = COPY %d0 %1(s64) = G_BITCAST %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: bitcast_s64_gpr_fpr name: bitcast_s64_gpr_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: bitcast_s64_gpr_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64all + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %d0 = COPY [[COPY1]] %0(s64) = COPY %x0 %1(s64) = G_BITCAST %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: bitcast_s64_fpr_gpr name: bitcast_s64_fpr_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: bitcast_s64_fpr_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %x0 = COPY [[COPY1]] %0(s64) = COPY %d0 %1(s64) = G_BITCAST %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: bitcast_s64_v2f32_fpr name: bitcast_s64_v2f32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: bitcast_s64_v2f32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %x0 = COPY [[COPY1]] %0(s64) = COPY %d0 %1(<2 x s32>) = G_BITCAST %0 %x0 = COPY %1(<2 x s32>) ... --- -# CHECK-LABEL: name: bitcast_s64_v8i8_fpr name: bitcast_s64_v8i8_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: bitcast_s64_v8i8_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %x0 = COPY [[COPY1]] %0(s64) = COPY %d0 %1(<8 x s8>) = G_BITCAST %0 %x0 = COPY %1(<8 x s8>) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir index 56a964f106c..d1118b64c52 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -8,52 +9,50 @@ ... --- -# CHECK-LABEL: name: bswap_s32 name: bswap_s32 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = REVWr %0 -# CHECK: %w0 = COPY %1 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: bswap_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[REVWr:%[0-9]+]] = REVWr [[COPY]] + ; CHECK: %w0 = COPY [[REVWr]] %0(s32) = COPY %w0 %1(s32) = G_BSWAP %0 %w0 = COPY %1 ... --- -# CHECK-LABEL: name: bswap_s64 name: bswap_s64 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = REVXr %0 -# CHECK: %x0 = COPY %1 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: bswap_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[REVXr:%[0-9]+]] = REVXr [[COPY]] + ; CHECK: %x0 = COPY [[REVXr]] %0(s64) = COPY %x0 %1(s64) = G_BSWAP %0 %x0 = COPY %1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir index 3b2f3746b58..1d38f4f759c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fma.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -7,31 +8,31 @@ ... --- -# CHECK-LABEL: name: FMADDSrrr_fpr name: FMADDSrrr_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } - { id: 2, class: fpr } - { id: 3, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = COPY %w2 -# CHECK: %3 = FMADDSrrr %0, %1, %2 body: | bb.0: liveins: %w0, %w1, %w2 + ; CHECK-LABEL: name: FMADDSrrr_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK-NEXT: id: 2, class: fpr32 + ; CHECK-NEXT: id: 3, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[COPY2:%[0-9]+]] = COPY %w2 + ; CHECK: [[FMADDSrrr:%[0-9]+]] = FMADDSrrr [[COPY]], [[COPY1]], [[COPY2]] + ; CHECK: %x0 = COPY [[FMADDSrrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = COPY %w2 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir index 3c343193557..f3c81e7d9c1 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-fp-casts.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -33,550 +34,550 @@ ... --- -# CHECK-LABEL: name: fptrunc_s16_s32_fpr name: fptrunc_s16_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK: - { id: 1, class: fpr16, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTHSr %0 body: | bb.0: liveins: %s0 + ; CHECK-LABEL: name: fptrunc_s16_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr16 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[FCVTHSr:%[0-9]+]] = FCVTHSr [[COPY]] + ; CHECK: %h0 = COPY [[FCVTHSr]] %0(s32) = COPY %s0 %1(s16) = G_FPTRUNC %0 %h0 = COPY %1(s16) ... --- -# CHECK-LABEL: name: fptrunc_s16_s64_fpr name: fptrunc_s16_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK: - { id: 1, class: fpr16, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTHDr %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: fptrunc_s16_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr16 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[FCVTHDr:%[0-9]+]] = FCVTHDr [[COPY]] + ; CHECK: %h0 = COPY [[FCVTHDr]] %0(s64) = COPY %d0 %1(s16) = G_FPTRUNC %0 %h0 = COPY %1(s16) ... --- -# CHECK-LABEL: name: fptrunc_s32_s64_fpr name: fptrunc_s32_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTSDr %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: fptrunc_s32_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[FCVTSDr:%[0-9]+]] = FCVTSDr [[COPY]] + ; CHECK: %s0 = COPY [[FCVTSDr]] %0(s64) = COPY %d0 %1(s32) = G_FPTRUNC %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: fpext_s32_s16_fpr name: fpext_s32_s16_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr16, preferred-register: '' } -# CHECK: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %h0 -# CHECK: %1 = FCVTSHr %0 body: | bb.0: liveins: %h0 + ; CHECK-LABEL: name: fpext_s32_s16_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr16 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %h0 + ; CHECK: [[FCVTSHr:%[0-9]+]] = FCVTSHr [[COPY]] + ; CHECK: %s0 = COPY [[FCVTSHr]] %0(s16) = COPY %h0 %1(s32) = G_FPEXT %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: fpext_s64_s16_fpr name: fpext_s64_s16_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr16, preferred-register: '' } -# CHECK: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %h0 -# CHECK: %1 = FCVTDHr %0 body: | bb.0: liveins: %h0 + ; CHECK-LABEL: name: fpext_s64_s16_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr16 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %h0 + ; CHECK: [[FCVTDHr:%[0-9]+]] = FCVTDHr [[COPY]] + ; CHECK: %d0 = COPY [[FCVTDHr]] %0(s16) = COPY %h0 %1(s64) = G_FPEXT %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: fpext_s64_s32_fpr name: fpext_s64_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTDSr %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: fpext_s64_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[FCVTDSr:%[0-9]+]] = FCVTDSr [[COPY]] + ; CHECK: %d0 = COPY [[FCVTDSr]] %0(s32) = COPY %s0 %1(s64) = G_FPEXT %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: sitofp_s32_s32_fpr name: sitofp_s32_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SCVTFUWSri %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: sitofp_s32_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SCVTFUWSri:%[0-9]+]] = SCVTFUWSri [[COPY]] + ; CHECK: %s0 = COPY [[SCVTFUWSri]] %0(s32) = COPY %w0 %1(s32) = G_SITOFP %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: sitofp_s32_s64_fpr name: sitofp_s32_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = SCVTFUXSri %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: sitofp_s32_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[SCVTFUXSri:%[0-9]+]] = SCVTFUXSri [[COPY]] + ; CHECK: %s0 = COPY [[SCVTFUXSri]] %0(s64) = COPY %x0 %1(s32) = G_SITOFP %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: sitofp_s64_s32_fpr name: sitofp_s64_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SCVTFUWDri %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: sitofp_s64_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SCVTFUWDri:%[0-9]+]] = SCVTFUWDri [[COPY]] + ; CHECK: %d0 = COPY [[SCVTFUWDri]] %0(s32) = COPY %w0 %1(s64) = G_SITOFP %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: sitofp_s64_s64_fpr name: sitofp_s64_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = SCVTFUXDri %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: sitofp_s64_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[SCVTFUXDri:%[0-9]+]] = SCVTFUXDri [[COPY]] + ; CHECK: %d0 = COPY [[SCVTFUXDri]] %0(s64) = COPY %x0 %1(s64) = G_SITOFP %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: uitofp_s32_s32_fpr name: uitofp_s32_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UCVTFUWSri %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: uitofp_s32_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[UCVTFUWSri:%[0-9]+]] = UCVTFUWSri [[COPY]] + ; CHECK: %s0 = COPY [[UCVTFUWSri]] %0(s32) = COPY %w0 %1(s32) = G_UITOFP %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: uitofp_s32_s64_fpr name: uitofp_s32_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = UCVTFUXSri %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: uitofp_s32_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[UCVTFUXSri:%[0-9]+]] = UCVTFUXSri [[COPY]] + ; CHECK: %s0 = COPY [[UCVTFUXSri]] %0(s64) = COPY %x0 %1(s32) = G_UITOFP %0 %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: uitofp_s64_s32_fpr name: uitofp_s64_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UCVTFUWDri %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: uitofp_s64_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[UCVTFUWDri:%[0-9]+]] = UCVTFUWDri [[COPY]] + ; CHECK: %d0 = COPY [[UCVTFUWDri]] %0(s32) = COPY %w0 %1(s64) = G_UITOFP %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: uitofp_s64_s64_fpr name: uitofp_s64_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = UCVTFUXDri %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: uitofp_s64_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[UCVTFUXDri:%[0-9]+]] = UCVTFUXDri [[COPY]] + ; CHECK: %d0 = COPY [[UCVTFUXDri]] %0(s64) = COPY %x0 %1(s64) = G_UITOFP %0 %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: fptosi_s32_s32_gpr name: fptosi_s32_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZSUWSr %0 body: | bb.0: liveins: %s0 + ; CHECK-LABEL: name: fptosi_s32_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[FCVTZSUWSr:%[0-9]+]] = FCVTZSUWSr [[COPY]] + ; CHECK: %w0 = COPY [[FCVTZSUWSr]] %0(s32) = COPY %s0 %1(s32) = G_FPTOSI %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: fptosi_s32_s64_gpr name: fptosi_s32_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZSUWDr %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: fptosi_s32_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[FCVTZSUWDr:%[0-9]+]] = FCVTZSUWDr [[COPY]] + ; CHECK: %w0 = COPY [[FCVTZSUWDr]] %0(s64) = COPY %d0 %1(s32) = G_FPTOSI %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: fptosi_s64_s32_gpr name: fptosi_s64_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZSUXSr %0 body: | bb.0: liveins: %s0 + ; CHECK-LABEL: name: fptosi_s64_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[FCVTZSUXSr:%[0-9]+]] = FCVTZSUXSr [[COPY]] + ; CHECK: %x0 = COPY [[FCVTZSUXSr]] %0(s32) = COPY %s0 %1(s64) = G_FPTOSI %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: fptosi_s64_s64_gpr name: fptosi_s64_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZSUXDr %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: fptosi_s64_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[FCVTZSUXDr:%[0-9]+]] = FCVTZSUXDr [[COPY]] + ; CHECK: %x0 = COPY [[FCVTZSUXDr]] %0(s64) = COPY %d0 %1(s64) = G_FPTOSI %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: fptoui_s32_s32_gpr name: fptoui_s32_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZUUWSr %0 body: | bb.0: liveins: %s0 + ; CHECK-LABEL: name: fptoui_s32_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[FCVTZUUWSr:%[0-9]+]] = FCVTZUUWSr [[COPY]] + ; CHECK: %w0 = COPY [[FCVTZUUWSr]] %0(s32) = COPY %s0 %1(s32) = G_FPTOUI %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: fptoui_s32_s64_gpr name: fptoui_s32_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZUUWDr %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: fptoui_s32_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[FCVTZUUWDr:%[0-9]+]] = FCVTZUUWDr [[COPY]] + ; CHECK: %w0 = COPY [[FCVTZUUWDr]] %0(s64) = COPY %d0 %1(s32) = G_FPTOUI %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: fptoui_s64_s32_gpr name: fptoui_s64_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %s0 -# CHECK: %1 = FCVTZUUXSr %0 body: | bb.0: liveins: %s0 + ; CHECK-LABEL: name: fptoui_s64_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr32 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %s0 + ; CHECK: [[FCVTZUUXSr:%[0-9]+]] = FCVTZUUXSr [[COPY]] + ; CHECK: %x0 = COPY [[FCVTZUUXSr]] %0(s32) = COPY %s0 %1(s64) = G_FPTOUI %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: fptoui_s64_s64_gpr name: fptoui_s64_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %1 = FCVTZUUXDr %0 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: fptoui_s64_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[FCVTZUUXDr:%[0-9]+]] = FCVTZUUXDr [[COPY]] + ; CHECK: %x0 = COPY [[FCVTZUUXDr]] %0(s64) = COPY %d0 %1(s64) = G_FPTOUI %0 %x0 = COPY %1(s64) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir index 1fc20ff98f7..a89adc27971 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-imm.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -10,44 +11,44 @@ --- # Check that we select a 32-bit immediate into a MOVi32imm. -# CHECK-LABEL: name: imm_s32_gpr name: imm_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } -# CHECK: body: -# CHECK: %0 = MOVi32imm -1234 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: imm_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK: [[MOVi32imm:%[0-9]+]] = MOVi32imm -1234 + ; CHECK: %w0 = COPY [[MOVi32imm]] %0(s32) = G_CONSTANT i32 -1234 %w0 = COPY %0(s32) ... --- # Check that we select a 64-bit immediate into a MOVi64imm. -# CHECK-LABEL: name: imm_s64_gpr name: imm_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } -# CHECK: body: -# CHECK: %0 = MOVi64imm 1234 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: imm_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK: [[MOVi64imm:%[0-9]+]] = MOVi64imm 1234 + ; CHECK: %w0 = COPY [[MOVi64imm]] %0(s64) = G_CONSTANT i64 1234 %w0 = COPY %0(s64) ... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir index 8604b2769ba..e2744e99d15 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-implicit-def.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -7,23 +8,22 @@ ... --- -# CHECK-LABEL: name: implicit_def name: implicit_def legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: [[DEF:%[0-9]+]] = IMPLICIT_DEF -# CHECK: [[ADD:%[0-9]+]] = ADDWrr [[DEF]], [[DEF]] -# CHECK: %w0 = COPY [[ADD]] body: | bb.0: + ; CHECK-LABEL: name: implicit_def + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[DEF:%[0-9]+]] = IMPLICIT_DEF + ; CHECK: [[ADDWrr:%[0-9]+]] = ADDWrr [[DEF]], [[DEF]] + ; CHECK: %w0 = COPY [[ADDWrr]] %0(s32) = G_IMPLICIT_DEF %1(s32) = G_ADD %0, %0 %w0 = COPY %1(s32) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir index 5f29f8b62fa..b7b7de4ae61 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ext.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -18,256 +19,256 @@ ... --- -# CHECK-LABEL: name: anyext_s64_from_s32 name: anyext_s64_from_s32 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64all, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = COPY %2 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: anyext_s64_from_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32all + ; CHECK-NEXT: id: 1, class: gpr64all + ; CHECK-NEXT: id: 2, class: gpr64all + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[SUBREG_TO_REG]] + ; CHECK: %x0 = COPY [[COPY1]] %0(s32) = COPY %w0 %1(s64) = G_ANYEXT %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: anyext_s32_from_s8 name: anyext_s32_from_s8 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32all, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32all, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: anyext_s32_from_s8 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32all + ; CHECK-NEXT: id: 1, class: gpr32all + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %w0 = COPY [[COPY1]] %0(s8) = COPY %w0 %1(s32) = G_ANYEXT %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: zext_s64_from_s32 name: zext_s64_from_s32 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = UBFMXri %2, 0, 31 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: zext_s64_from_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15 + ; CHECK: [[UBFMXri:%[0-9]+]] = UBFMXri [[SUBREG_TO_REG]], 0, 31 + ; CHECK: %x0 = COPY [[UBFMXri]] %0(s32) = COPY %w0 %1(s64) = G_ZEXT %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: zext_s32_from_s16 name: zext_s32_from_s16 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UBFMWri %0, 0, 15 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: zext_s32_from_s16 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 15 + ; CHECK: %w0 = COPY [[UBFMWri]] %0(s16) = COPY %w0 %1(s32) = G_ZEXT %0 %w0 = COPY %1 ... --- -# CHECK-LABEL: name: zext_s32_from_s8 name: zext_s32_from_s8 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UBFMWri %0, 0, 7 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: zext_s32_from_s8 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 7 + ; CHECK: %w0 = COPY [[UBFMWri]] %0(s8) = COPY %w0 %1(s32) = G_ZEXT %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: zext_s16_from_s8 name: zext_s16_from_s8 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = UBFMWri %0, 0, 7 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: zext_s16_from_s8 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[UBFMWri:%[0-9]+]] = UBFMWri [[COPY]], 0, 7 + ; CHECK: %w0 = COPY [[UBFMWri]] %0(s8) = COPY %w0 %1(s16) = G_ZEXT %0 %w0 = COPY %1(s16) ... --- -# CHECK-LABEL: name: sext_s64_from_s32 name: sext_s64_from_s32 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = SUBREG_TO_REG 0, %0, 15 -# CHECK: %1 = SBFMXri %2, 0, 31 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: sext_s64_from_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SUBREG_TO_REG:%[0-9]+]] = SUBREG_TO_REG 0, [[COPY]], 15 + ; CHECK: [[SBFMXri:%[0-9]+]] = SBFMXri [[SUBREG_TO_REG]], 0, 31 + ; CHECK: %x0 = COPY [[SBFMXri]] %0(s32) = COPY %w0 %1(s64) = G_SEXT %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: sext_s32_from_s16 name: sext_s32_from_s16 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SBFMWri %0, 0, 15 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: sext_s32_from_s16 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 15 + ; CHECK: %w0 = COPY [[SBFMWri]] %0(s16) = COPY %w0 %1(s32) = G_SEXT %0 %w0 = COPY %1 ... --- -# CHECK-LABEL: name: sext_s32_from_s8 name: sext_s32_from_s8 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SBFMWri %0, 0, 7 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: sext_s32_from_s8 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 7 + ; CHECK: %w0 = COPY [[SBFMWri]] %0(s8) = COPY %w0 %1(s32) = G_SEXT %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: sext_s16_from_s8 name: sext_s16_from_s8 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = SBFMWri %0, 0, 7 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: sext_s16_from_s8 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[SBFMWri:%[0-9]+]] = SBFMWri [[COPY]], 0, 7 + ; CHECK: %w0 = COPY [[SBFMWri]] %0(s8) = COPY %w0 %1(s16) = G_SEXT %0 %w0 = COPY %1(s16) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir index b71a9a3d731..585664649d8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -12,138 +13,138 @@ ... --- -# CHECK-LABEL: name: inttoptr_p0_s64 name: inttoptr_p0_s64 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64all, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64all, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: inttoptr_p0_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64all + ; CHECK-NEXT: id: 1, class: gpr64all + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %x0 = COPY [[COPY1]] %0(s64) = COPY %x0 %1(p0) = G_INTTOPTR %0 %x0 = COPY %1(p0) ... --- -# CHECK-LABEL: name: ptrtoint_s64_p0 name: ptrtoint_s64_p0 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: ptrtoint_s64_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %x0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s64) = G_PTRTOINT %0 %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: ptrtoint_s32_p0 name: ptrtoint_s32_p0 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: ptrtoint_s32_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s32) = G_PTRTOINT %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: ptrtoint_s16_p0 name: ptrtoint_s16_p0 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: ptrtoint_s16_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s16) = G_PTRTOINT %0 %w0 = COPY %1(s16) ... --- -# CHECK-LABEL: name: ptrtoint_s8_p0 name: ptrtoint_s8_p0 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: ptrtoint_s8_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s8) = G_PTRTOINT %0 %w0 = COPY %1(s8) ... --- -# CHECK-LABEL: name: ptrtoint_s1_p0 name: ptrtoint_s1_p0 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %0.sub_32 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: ptrtoint_s1_p0 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 + ; CHECK: %w0 = COPY [[COPY1]] %0(p0) = COPY %x0 %1(s1) = G_PTRTOINT %0 %w0 = COPY %1(s1) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir index 43e682c6b6c..7f0fc2cad6f 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-intrinsic-aarch64-sdiv.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -9,28 +10,28 @@ --- # Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32. # Also check that we constrain the register class of the COPY to GPR32. -# CHECK-LABEL: name: sdiv_s32_gpr name: sdiv_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = SDIVWr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: sdiv_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[SDIVWr:%[0-9]+]] = SDIVWr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[SDIVWr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir index 2955788a71e..801ba35bd4c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -32,114 +33,110 @@ ... --- -# CHECK-LABEL: name: load_s64_gpr name: load_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRXui %0, 0 :: (load 8 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]] = LDRXui [[COPY]], 0 :: (load 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] %0(p0) = COPY %x0 %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: load_s32_gpr name: load_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRWui %0, 0 :: (load 4 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRWui:%[0-9]+]] = LDRWui [[COPY]], 0 :: (load 4 from %ir.addr) + ; CHECK: %w0 = COPY [[LDRWui]] %0(p0) = COPY %x0 %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: load_s16_gpr name: load_s16_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRHHui %0, 0 :: (load 2 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s16_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr) + ; CHECK: %w0 = COPY [[LDRHHui]] %0(p0) = COPY %x0 %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) %w0 = COPY %1(s16) ... --- -# CHECK-LABEL: name: load_s8_gpr name: load_s8_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRBBui %0, 0 :: (load 1 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s8_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr) + ; CHECK: %w0 = COPY [[LDRBBui]] %0(p0) = COPY %x0 %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %w0 = COPY %1(s8) ... --- -# CHECK-LABEL: name: load_fi_s64_gpr name: load_fi_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -147,43 +144,45 @@ registers: stack: - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } -# CHECK: body: -# CHECK: %1 = LDRXui %stack.0.ptr0, 0 :: (load 8) -# CHECK: %x0 = COPY %1 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_fi_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[LDRXui:%[0-9]+]] = LDRXui %stack.0.ptr0, 0 :: (load 8) + ; CHECK: %x0 = COPY [[LDRXui]] %0(p0) = G_FRAME_INDEX %stack.0.ptr0 %1(s64) = G_LOAD %0 :: (load 8) %x0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: load_gep_128_s64_gpr name: load_gep_128_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRXui %0, 16 :: (load 8 from %ir.addr) -# CHECK: %x0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_128_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRXui:%[0-9]+]] = LDRXui [[COPY]], 16 :: (load 8 from %ir.addr) + ; CHECK: %x0 = COPY [[LDRXui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 128 %2(p0) = G_GEP %0, %1 @@ -192,30 +191,29 @@ body: | ... --- -# CHECK-LABEL: name: load_gep_512_s32_gpr name: load_gep_512_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRWui %0, 128 :: (load 4 from %ir.addr) -# CHECK: %w0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_512_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRWui:%[0-9]+]] = LDRWui [[COPY]], 128 :: (load 4 from %ir.addr) + ; CHECK: %w0 = COPY [[LDRWui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 512 %2(p0) = G_GEP %0, %1 @@ -224,30 +222,29 @@ body: | ... --- -# CHECK-LABEL: name: load_gep_64_s16_gpr name: load_gep_64_s16_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRHHui %0, 32 :: (load 2 from %ir.addr) -# CHECK: %w0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_64_s16_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRHHui:%[0-9]+]] = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr) + ; CHECK: %w0 = COPY [[LDRHHui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 64 %2(p0) = G_GEP %0, %1 @@ -256,30 +253,29 @@ body: | ... --- -# CHECK-LABEL: name: load_gep_1_s8_gpr name: load_gep_1_s8_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRBBui %0, 1 :: (load 1 from %ir.addr) -# CHECK: %w0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_1_s8_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRBBui:%[0-9]+]] = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr) + ; CHECK: %w0 = COPY [[LDRBBui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 1 %2(p0) = G_GEP %0, %1 @@ -288,130 +284,129 @@ body: | ... --- -# CHECK-LABEL: name: load_s64_fpr name: load_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr) + ; CHECK: %d0 = COPY [[LDRDui]] %0(p0) = COPY %x0 %1(s64) = G_LOAD %0 :: (load 8 from %ir.addr) %d0 = COPY %1(s64) ... --- -# CHECK-LABEL: name: load_s32_fpr name: load_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRSui %0, 0 :: (load 4 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRSui:%[0-9]+]] = LDRSui [[COPY]], 0 :: (load 4 from %ir.addr) + ; CHECK: %s0 = COPY [[LDRSui]] %0(p0) = COPY %x0 %1(s32) = G_LOAD %0 :: (load 4 from %ir.addr) %s0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: load_s16_fpr name: load_s16_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr16, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRHui %0, 0 :: (load 2 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s16_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr16 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRHui:%[0-9]+]] = LDRHui [[COPY]], 0 :: (load 2 from %ir.addr) + ; CHECK: %h0 = COPY [[LDRHui]] %0(p0) = COPY %x0 %1(s16) = G_LOAD %0 :: (load 2 from %ir.addr) %h0 = COPY %1(s16) ... --- -# CHECK-LABEL: name: load_s8_fpr name: load_s8_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRBui %0, 0 :: (load 1 from %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_s8_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr8 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRBui:%[0-9]+]] = LDRBui [[COPY]], 0 :: (load 1 from %ir.addr) + ; CHECK: %b0 = COPY [[LDRBui]] %0(p0) = COPY %x0 %1(s8) = G_LOAD %0 :: (load 1 from %ir.addr) %b0 = COPY %1(s8) ... --- -# CHECK-LABEL: name: load_gep_8_s64_fpr name: load_gep_8_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRDui %0, 1 :: (load 8 from %ir.addr) -# CHECK: %d0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_8_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 1 :: (load 8 from %ir.addr) + ; CHECK: %d0 = COPY [[LDRDui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 8 %2(p0) = G_GEP %0, %1 @@ -420,30 +415,29 @@ body: | ... --- -# CHECK-LABEL: name: load_gep_16_s32_fpr name: load_gep_16_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRSui %0, 4 :: (load 4 from %ir.addr) -# CHECK: %s0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_16_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRSui:%[0-9]+]] = LDRSui [[COPY]], 4 :: (load 4 from %ir.addr) + ; CHECK: %s0 = COPY [[LDRSui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 16 %2(p0) = G_GEP %0, %1 @@ -452,30 +446,29 @@ body: | ... --- -# CHECK-LABEL: name: load_gep_64_s16_fpr name: load_gep_64_s16_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: fpr16, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRHui %0, 32 :: (load 2 from %ir.addr) -# CHECK: %h0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_64_s16_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: fpr16 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRHui:%[0-9]+]] = LDRHui [[COPY]], 32 :: (load 2 from %ir.addr) + ; CHECK: %h0 = COPY [[LDRHui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 64 %2(p0) = G_GEP %0, %1 @@ -484,30 +477,29 @@ body: | ... --- -# CHECK-LABEL: name: load_gep_32_s8_fpr name: load_gep_32_s8_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: fpr8, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %3 = LDRBui %0, 32 :: (load 1 from %ir.addr) -# CHECK: %b0 = COPY %3 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_gep_32_s8_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: fpr8 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRBui:%[0-9]+]] = LDRBui [[COPY]], 32 :: (load 1 from %ir.addr) + ; CHECK: %b0 = COPY [[LDRBui]] %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 32 %2(p0) = G_GEP %0, %1 @@ -515,26 +507,25 @@ body: | %b0 = COPY %3 ... --- -# CHECK-LABEL: name: load_v2s32 name: load_v2s32 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = LDRDui %0, 0 :: (load 8 from %ir.addr) -# CHECK: %d0 = COPY %1 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: load_v2s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[LDRDui:%[0-9]+]] = LDRDui [[COPY]], 0 :: (load 8 from %ir.addr) + ; CHECK: %d0 = COPY [[LDRDui]] %0(p0) = COPY %x0 %1(<2 x s32>) = G_LOAD %0 :: (load 8 from %ir.addr) %d0 = COPY %1(<2 x s32>) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir index cd7a79f17d9..119812575c5 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-muladd.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -7,19 +8,10 @@ ... --- -# CHECK-LABEL: name: SMADDLrrr_gpr name: SMADDLrrr_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 4, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 5, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 6, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -29,15 +21,24 @@ registers: - { id: 5, class: gpr } - { id: 6, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = COPY %w2 -# CHECK: %6 = SMADDLrrr %1, %2, %0 body: | bb.0: liveins: %x0, %w1, %w2 + ; CHECK-LABEL: name: SMADDLrrr_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK-NEXT: id: 4, class: gpr + ; CHECK-NEXT: id: 5, class: gpr + ; CHECK-NEXT: id: 6, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[COPY2:%[0-9]+]] = COPY %w2 + ; CHECK: [[SMADDLrrr:%[0-9]+]] = SMADDLrrr [[COPY1]], [[COPY2]], [[COPY]] + ; CHECK: %x0 = COPY [[SMADDLrrr]] %0(s64) = COPY %x0 %1(s32) = COPY %w1 %2(s32) = COPY %w2 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir index a7a33acab25..4c3b069e88a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-neon-vcvtfxu2fp.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -mattr=+neon,+fullfp16 -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -8,28 +9,27 @@ --- # Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64. -# CHECK-LABEL: name: vcvtfxu2fp_s64_fpr name: vcvtfxu2fp_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: fpr64, preferred-register: '' } registers: - { id: 0, class: fpr } - { id: 1, class: gpr } - { id: 2, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %d0 -# CHECK: %2 = UCVTFd %0, 12 -# CHECK: %d1 = COPY %2 body: | bb.0: liveins: %d0 + ; CHECK-LABEL: name: vcvtfxu2fp_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: fpr64 + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %d0 + ; CHECK: [[UCVTFd:%[0-9]+]] = UCVTFd [[COPY]], 12 + ; CHECK: %d1 = COPY [[UCVTFd]] %0(s64) = COPY %d0 %1(s32) = G_CONSTANT i32 12 %2(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.vcvtfxu2fp.f64), %0, %1 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir index 536e236c273..38eeb7f8060 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -29,26 +30,25 @@ ... --- -# CHECK-LABEL: name: store_s64_gpr name: store_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: STRXui %1, %0, 0 :: (store 8 into %ir.addr) body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: store_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: STRXui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr) %0(p0) = COPY %x0 %1(s64) = COPY %x1 G_STORE %1, %0 :: (store 8 into %ir.addr) @@ -56,26 +56,25 @@ body: | ... --- -# CHECK-LABEL: name: store_s32_gpr name: store_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRWui %1, %0, 0 :: (store 4 into %ir.addr) body: | bb.0: liveins: %x0, %w1 + ; CHECK-LABEL: name: store_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: STRWui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr) %0(p0) = COPY %x0 %1(s32) = COPY %w1 G_STORE %1, %0 :: (store 4 into %ir.addr) @@ -83,26 +82,25 @@ body: | ... --- -# CHECK-LABEL: name: store_s16_gpr name: store_s16_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRHHui %1, %0, 0 :: (store 2 into %ir.addr) body: | bb.0: liveins: %x0, %w1 + ; CHECK-LABEL: name: store_s16_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store 2 into %ir.addr) %0(p0) = COPY %x0 %1(s16) = COPY %w1 G_STORE %1, %0 :: (store 2 into %ir.addr) @@ -110,26 +108,25 @@ body: | ... --- -# CHECK-LABEL: name: store_s8_gpr name: store_s8_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRBBui %1, %0, 0 :: (store 1 into %ir.addr) body: | bb.0: liveins: %x0, %w1 + ; CHECK-LABEL: name: store_s8_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store 1 into %ir.addr) %0(p0) = COPY %x0 %1(s8) = COPY %w1 G_STORE %1, %0 :: (store 1 into %ir.addr) @@ -137,25 +134,24 @@ body: | ... --- -# CHECK-LABEL: name: store_zero_s64_gpr name: store_zero_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: STRXui %xzr, %0, 0 :: (store 8 into %ir.addr) body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: store_zero_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: STRXui %xzr, [[COPY]], 0 :: (store 8 into %ir.addr) %0(p0) = COPY %x0 %1(s64) = G_CONSTANT i64 0 G_STORE %1, %0 :: (store 8 into %ir.addr) @@ -163,25 +159,24 @@ body: | ... --- -# CHECK-LABEL: name: store_zero_s32_gpr name: store_zero_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: STRWui %wzr, %0, 0 :: (store 4 into %ir.addr) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: store_zero_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: STRWui %wzr, [[COPY]], 0 :: (store 4 into %ir.addr) %0(p0) = COPY %x0 %1(s32) = G_CONSTANT i32 0 G_STORE %1, %0 :: (store 4 into %ir.addr) @@ -189,14 +184,10 @@ body: | ... --- -# CHECK-LABEL: name: store_fi_s64_gpr name: store_fi_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } @@ -204,43 +195,45 @@ registers: stack: - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: STRXui %0, %stack.0.ptr0, 0 :: (store 8) body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: store_fi_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: STRXui [[COPY]], %stack.0.ptr0, 0 :: (store 8) %0(p0) = COPY %x0 %1(p0) = G_FRAME_INDEX %stack.0.ptr0 G_STORE %0, %1 :: (store 8) ... --- -# CHECK-LABEL: name: store_gep_128_s64_gpr name: store_gep_128_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: STRXui %1, %0, 16 :: (store 8 into %ir.addr) body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: store_gep_128_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: STRXui [[COPY1]], [[COPY]], 16 :: (store 8 into %ir.addr) %0(p0) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_CONSTANT i64 128 @@ -249,30 +242,29 @@ body: | ... --- -# CHECK-LABEL: name: store_gep_512_s32_gpr name: store_gep_512_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRWui %1, %0, 128 :: (store 4 into %ir.addr) body: | bb.0: liveins: %x0, %w1 + ; CHECK-LABEL: name: store_gep_512_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: STRWui [[COPY1]], [[COPY]], 128 :: (store 4 into %ir.addr) %0(p0) = COPY %x0 %1(s32) = COPY %w1 %2(s64) = G_CONSTANT i64 512 @@ -281,30 +273,29 @@ body: | ... --- -# CHECK-LABEL: name: store_gep_64_s16_gpr name: store_gep_64_s16_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRHHui %1, %0, 32 :: (store 2 into %ir.addr) body: | bb.0: liveins: %x0, %w1 + ; CHECK-LABEL: name: store_gep_64_s16_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store 2 into %ir.addr) %0(p0) = COPY %x0 %1(s16) = COPY %w1 %2(s64) = G_CONSTANT i64 64 @@ -313,30 +304,29 @@ body: | ... --- -# CHECK-LABEL: name: store_gep_1_s8_gpr name: store_gep_1_s8_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %w1 -# CHECK: STRBBui %1, %0, 1 :: (store 1 into %ir.addr) body: | bb.0: liveins: %x0, %w1 + ; CHECK-LABEL: name: store_gep_1_s8_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store 1 into %ir.addr) %0(p0) = COPY %x0 %1(s8) = COPY %w1 %2(s64) = G_CONSTANT i64 1 @@ -345,26 +335,25 @@ body: | ... --- -# CHECK-LABEL: name: store_s64_fpr name: store_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %d1 -# CHECK: STRDui %1, %0, 0 :: (store 8 into %ir.addr) body: | bb.0: liveins: %x0, %d1 + ; CHECK-LABEL: name: store_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1 + ; CHECK: STRDui [[COPY1]], [[COPY]], 0 :: (store 8 into %ir.addr) %0(p0) = COPY %x0 %1(s64) = COPY %d1 G_STORE %1, %0 :: (store 8 into %ir.addr) @@ -372,26 +361,25 @@ body: | ... --- -# CHECK-LABEL: name: store_s32_fpr name: store_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %s1 -# CHECK: STRSui %1, %0, 0 :: (store 4 into %ir.addr) body: | bb.0: liveins: %x0, %s1 + ; CHECK-LABEL: name: store_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1 + ; CHECK: STRSui [[COPY1]], [[COPY]], 0 :: (store 4 into %ir.addr) %0(p0) = COPY %x0 %1(s32) = COPY %s1 G_STORE %1, %0 :: (store 4 into %ir.addr) @@ -399,30 +387,29 @@ body: | ... --- -# CHECK-LABEL: name: store_gep_8_s64_fpr name: store_gep_8_s64_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %d1 -# CHECK: STRDui %1, %0, 1 :: (store 8 into %ir.addr) body: | bb.0: liveins: %x0, %d1 + ; CHECK-LABEL: name: store_gep_8_s64_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr64 + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %d1 + ; CHECK: STRDui [[COPY1]], [[COPY]], 1 :: (store 8 into %ir.addr) %0(p0) = COPY %x0 %1(s64) = COPY %d1 %2(s64) = G_CONSTANT i64 8 @@ -431,30 +418,29 @@ body: | ... --- -# CHECK-LABEL: name: store_gep_8_s32_fpr name: store_gep_8_s32_fpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: fpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 3, class: gpr, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: fpr } - { id: 2, class: gpr } - { id: 3, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %s1 -# CHECK: STRSui %1, %0, 2 :: (store 4 into %ir.addr) body: | bb.0: liveins: %x0, %s1 + ; CHECK-LABEL: name: store_gep_8_s32_fpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: fpr32 + ; CHECK-NEXT: id: 2, class: gpr + ; CHECK-NEXT: id: 3, class: gpr + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %s1 + ; CHECK: STRSui [[COPY1]], [[COPY]], 2 :: (store 4 into %ir.addr) %0(p0) = COPY %x0 %1(s32) = COPY %s1 %2(s64) = G_CONSTANT i64 8 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir index f43a9ab34ff..1d6664402e8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -9,72 +10,75 @@ ... --- -# CHECK-LABEL: name: trunc_s32_s64 name: trunc_s32_s64 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64sp, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32sp, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %1 = COPY %0.sub_32 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: trunc_s32_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64sp + ; CHECK-NEXT: id: 1, class: gpr32sp + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 + ; CHECK: %w0 = COPY [[COPY1]] %0(s64) = COPY %x0 %1(s32) = G_TRUNC %0 %w0 = COPY %1(s32) ... --- -# CHECK-LABEL: name: trunc_s8_s64 name: trunc_s8_s64 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %1 = COPY %0.sub_32 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: trunc_s8_s64 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]].sub_32 + ; CHECK: %w0 = COPY [[COPY1]] %0(s64) = COPY %x0 %1(s8) = G_TRUNC %0 %w0 = COPY %1(s8) ... --- -# CHECK-LABEL: name: trunc_s1_s32 name: trunc_s1_s32 legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } -# CHECK: body: -# CHECK: %1 = COPY %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: trunc_s1_s32 + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY [[COPY]] + ; CHECK: %w0 = COPY [[COPY1]] %0(s32) = COPY %w0 %1(s1) = G_TRUNC %0 %w0 = COPY %1(s1) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir index 7190fda15b8..ec6b1e4c8c9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-xor.mir @@ -1,3 +1,4 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s --- | @@ -14,28 +15,28 @@ --- # Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32. # Also check that we constrain the register class of the COPY to GPR32. -# CHECK-LABEL: name: xor_s32_gpr name: xor_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %1 = COPY %w1 -# CHECK: %2 = EORWrr %0, %1 body: | bb.0: liveins: %w0, %w1 + ; CHECK-LABEL: name: xor_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr32 + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %w1 + ; CHECK: [[EORWrr:%[0-9]+]] = EORWrr [[COPY]], [[COPY1]] + ; CHECK: %w0 = COPY [[EORWrr]] %0(s32) = COPY %w0 %1(s32) = COPY %w1 %2(s32) = G_XOR %0, %1 @@ -44,28 +45,28 @@ body: | --- # Same as xor_s64_gpr, for 64-bit operations. -# CHECK-LABEL: name: xor_s64_gpr name: xor_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %1 = COPY %x1 -# CHECK: %2 = EORXrr %0, %1 body: | bb.0: liveins: %x0, %x1 + ; CHECK-LABEL: name: xor_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr64 + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[COPY1:%[0-9]+]] = COPY %x1 + ; CHECK: [[EORXrr:%[0-9]+]] = EORXrr [[COPY]], [[COPY1]] + ; CHECK: %x0 = COPY [[EORXrr]] %0(s64) = COPY %x0 %1(s64) = COPY %x1 %2(s64) = G_XOR %0, %1 @@ -75,27 +76,27 @@ body: | --- # Check that we select a 32-bit GPR G_XOR into EORWrr on GPR32. # Also check that we constrain the register class of the COPY to GPR32. -# CHECK-LABEL: name: xor_constant_n1_s32_gpr name: xor_constant_n1_s32_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %w0 -# CHECK: %2 = ORNWrr %wzr, %0 body: | bb.0: liveins: %w0 + ; CHECK-LABEL: name: xor_constant_n1_s32_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[ORNWrr:%[0-9]+]] = ORNWrr %wzr, [[COPY]] + ; CHECK: %w0 = COPY [[ORNWrr]] %0(s32) = COPY %w0 %1(s32) = G_CONSTANT i32 -1 %2(s32) = G_XOR %0, %1 @@ -104,27 +105,27 @@ body: | --- # Same as xor_constant_n1_s64_gpr, for 64-bit operations. -# CHECK-LABEL: name: xor_constant_n1_s64_gpr name: xor_constant_n1_s64_gpr legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr64, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr64, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: %0 = COPY %x0 -# CHECK: %2 = ORNXrr %xzr, %0 body: | bb.0: liveins: %x0 + ; CHECK-LABEL: name: xor_constant_n1_s64_gpr + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr64 + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr64 + ; CHECK: [[COPY:%[0-9]+]] = COPY %x0 + ; CHECK: [[ORNXrr:%[0-9]+]] = ORNXrr %xzr, [[COPY]] + ; CHECK: %x0 = COPY [[ORNXrr]] %0(s64) = COPY %x0 %1(s64) = G_CONSTANT i64 -1 %2(s64) = G_XOR %0, %1 @@ -133,26 +134,29 @@ body: | --- # Check that we can obtain constants from other basic blocks. -# CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb name: xor_constant_n1_s32_gpr_2bb legalized: true regBankSelected: true -# CHECK: registers: -# CHECK-NEXT: - { id: 0, class: gpr32, preferred-register: '' } -# CHECK-NEXT: - { id: 1, class: gpr, preferred-register: '' } -# CHECK-NEXT: - { id: 2, class: gpr32, preferred-register: '' } registers: - { id: 0, class: gpr } - { id: 1, class: gpr } - { id: 2, class: gpr } -# CHECK: body: -# CHECK: B %bb.1 -# CHECK: %0 = COPY %w0 -# CHECK: %2 = ORNWrr %wzr, %0 body: | + ; CHECK-LABEL: name: xor_constant_n1_s32_gpr_2bb + ; CHECK: registers: + ; CHECK-NEXT: id: 0, class: gpr32 + ; CHECK-NEXT: id: 1, class: gpr + ; CHECK-NEXT: id: 2, class: gpr32 + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: B %bb.1 + ; CHECK: bb.1: + ; CHECK: [[COPY:%[0-9]+]] = COPY %w0 + ; CHECK: [[ORNWrr:%[0-9]+]] = ORNWrr %wzr, [[COPY]] + ; CHECK: %w0 = COPY [[ORNWrr]] bb.0: liveins: %w0, %w1 successors: %bb.1 |
