diff options
Diffstat (limited to 'llvm/lib/Target')
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedBroadwell.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedHaswell.td | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 3 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 3 |
5 files changed, 5 insertions, 16 deletions
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 934a545c079..a878f1d765b 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -401,8 +401,7 @@ def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> { def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr", "BLSI(32|64)rr", "BLSMSK(32|64)rr", - "BLSR(32|64)rr", - "LEA(16|32|64)(_32)?r")>; + "BLSR(32|64)rr")>; def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 80a626ce688..b9f9c8c485a 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -745,8 +745,7 @@ def HWWriteResGroup8 : SchedWriteRes<[HWPort15]> { def: InstRW<[HWWriteResGroup8], (instregex "ANDN(32|64)rr", "BLSI(32|64)rr", "BLSMSK(32|64)rr", - "BLSR(32|64)rr", - "LEA(16|32|64)(_32)?r")>; + "BLSR(32|64)rr")>; def HWWriteResGroup9 : SchedWriteRes<[HWPort015]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index bc9ec5765e8..eca97110bcc 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -120,7 +120,7 @@ def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> { // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. -def : WriteRes<WriteLEA, [SBPort15]>; +def : WriteRes<WriteLEA, [SBPort01]>; // Bit counts. defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>; @@ -341,13 +341,6 @@ def: InstRW<[SBWriteResGroup2], (instregex "FFREE", "(V?)MOV64toPQIrr", "(V?)MOVDI2PDIrr")>; -def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>; - def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { let Latency = 1; let NumMicroOps = 1; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 1665527f7c6..02c8bd83013 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -485,8 +485,7 @@ def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr", "BLSI(32|64)rr", "BLSMSK(32|64)rr", - "BLSR(32|64)rr", - "LEA(16|32|64)(_32)?r")>; + "BLSR(32|64)rr")>; def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { let Latency = 1; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 049edf638c3..21632fcdaff 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -790,8 +790,7 @@ def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr", "BLSI(32|64)rr", "BLSMSK(32|64)rr", - "BLSR(32|64)rr", - "LEA(16|32|64)(_32)?r")>; + "BLSR(32|64)rr")>; def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { let Latency = 1; |
