diff options
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSandyBridge.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index bc9ec5765e8..eca97110bcc 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -120,7 +120,7 @@ def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> { // This is for simple LEAs with one or two input operands. // The complex ones can only execute on port 1, and they require two cycles on // the port to read all inputs. We don't model that. -def : WriteRes<WriteLEA, [SBPort15]>; +def : WriteRes<WriteLEA, [SBPort01]>; // Bit counts. defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>; @@ -341,13 +341,6 @@ def: InstRW<[SBWriteResGroup2], (instregex "FFREE", "(V?)MOV64toPQIrr", "(V?)MOVDI2PDIrr")>; -def SBWriteResGroup3 : SchedWriteRes<[SBPort01]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SBWriteResGroup3], (instregex "LEA(16|32|64)(_32)?r")>; - def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { let Latency = 1; let NumMicroOps = 1; |
