5 files changed, 24 insertions, 14 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index db7e751e060..83de2c2c150 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1172,9 +1172,11 @@ unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
 
 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
                                                     int &FrameIndex) const {
-  SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+  SmallVector<const MachineMemOperand *, 1> Accesses;
   if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses)) {
-    FrameIndex = Accesses.begin()->FI;
+    FrameIndex =
+        cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+            ->getFrameIndex();
     return true;
   }
   return false;
@@ -1390,9 +1392,11 @@ unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
 
 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
                                                      int &FrameIndex) const {
-  SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+  SmallVector<const MachineMemOperand *, 1> Accesses;
   if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses)) {
-    FrameIndex = Accesses.begin()->FI;
+    FrameIndex =
+        cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+            ->getFrameIndex();
     return true;
   }
   return false;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 20ed6a995f2..a3c160d01f8 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -337,7 +337,7 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
 /// operand of that instruction if true.
 bool HexagonInstrInfo::hasLoadFromStackSlot(
     const MachineInstr &MI,
-    SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
+    SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
   if (MI.isBundle()) {
     const MachineBasicBlock *MBB = MI.getParent();
     MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
@@ -355,7 +355,7 @@ bool HexagonInstrInfo::hasLoadFromStackSlot(
 /// operand of that instruction if true.
 bool HexagonInstrInfo::hasStoreToStackSlot(
     const MachineInstr &MI,
-    SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
+    SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
   if (MI.isBundle()) {
     const MachineBasicBlock *MBB = MI.getParent();
     MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index d2125fc6852..fe4a2f3662e 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -71,14 +71,14 @@ public:
   /// if true.
   bool hasLoadFromStackSlot(
       const MachineInstr &MI,
-      SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const override;
+      SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
 
   /// Check if the instruction or the bundle of instructions has
   /// store to stack slots. Return the frameindex and machine memory operand
   /// if true.
   bool hasStoreToStackSlot(
       const MachineInstr &MI,
-      SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const override;
+      SmallVectorImpl<const MachineMemOperand *> &Accesses) const override;
 
   /// Analyze the branching code at the end of MBB, returning
   /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
index 398c84a2a19..a18352738e1 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
+++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
@@ -733,9 +733,11 @@ unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
       return Reg;
     // Check for post-frame index elimination operations
-    SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+    SmallVector<const MachineMemOperand *, 1> Accesses;
     if (hasLoadFromStackSlot(MI, Accesses)){
-      FrameIndex = Accesses.begin()->FI;
+      FrameIndex =
+          cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+              ->getFrameIndex();
       return 1;
     }
   }
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 06a4d1f86ce..415ef7d8391 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -411,9 +411,11 @@ unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
       return Reg;
     // Check for post-frame index elimination operations
-    SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+    SmallVector<const MachineMemOperand *, 1> Accesses;
     if (hasLoadFromStackSlot(MI, Accesses)) {
-      FrameIndex = Accesses.begin()->FI;
+      FrameIndex =
+          cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+              ->getFrameIndex();
       return 1;
     }
   }
@@ -444,9 +446,11 @@ unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
       return Reg;
     // Check for post-frame index elimination operations
-    SmallVector<TargetInstrInfo::FrameAccess, 1> Accesses;
+    SmallVector<const MachineMemOperand *, 1> Accesses;
     if (hasStoreToStackSlot(MI, Accesses)) {
-      FrameIndex = Accesses.begin()->FI;
+      FrameIndex =
+          cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue())
+              ->getFrameIndex();
       return 1;
     }
   }