summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 20ed6a995f2..a3c160d01f8 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -337,7 +337,7 @@ unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
/// operand of that instruction if true.
bool HexagonInstrInfo::hasLoadFromStackSlot(
const MachineInstr &MI,
- SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
+ SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
if (MI.isBundle()) {
const MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
@@ -355,7 +355,7 @@ bool HexagonInstrInfo::hasLoadFromStackSlot(
/// operand of that instruction if true.
bool HexagonInstrInfo::hasStoreToStackSlot(
const MachineInstr &MI,
- SmallVectorImpl<TargetInstrInfo::FrameAccess> &Accesses) const {
+ SmallVectorImpl<const MachineMemOperand *> &Accesses) const {
if (MI.isBundle()) {
const MachineBasicBlock *MBB = MI.getParent();
MachineBasicBlock::const_instr_iterator MII = MI.getIterator();
OpenPOWER on IntegriCloud