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-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1351751613a..becf658956d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33155,7 +33155,7 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
// Only do this on the last DAG combine as it can interfere with other
// combines.
- if (!DCI.isAfterLegalizeVectorOps())
+ if (!DCI.isAfterLegalizeDAG())
return SDValue();
// Try to improve a sequence of srl (and X, C1), C2 by inverting the order.
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