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authorCraig Topper <craig.topper@intel.com>2018-03-06 19:44:52 +0000
committerCraig Topper <craig.topper@intel.com>2018-03-06 19:44:52 +0000
commit80d3bb3b4be2cc0d3ad25530a83c94ae9c5d1ba7 (patch)
treef2356db1943a3a27e7d2dc758d5621e28766d3b4 /llvm/lib/Target/X86/X86ISelLowering.cpp
parent091f9eb963c63f4b68ed46725c82e63c21ba0606 (diff)
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[TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner::isAfterLegalizeDAG since that's what it checks. NFC
The code checks Level == AfterLegalizeDAG which is the fourth and last of the possible DAG combine stages that we have. There is a Level called AfterLegalVectorOps, but that's the third DAG combine and it doesn't always run. A function called isAfterLegalVectorOps should imply it returns true in either of the DAG combines that runs after the legalize vector ops stage, but that's not what this function does. llvm-svn: 326832
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 1351751613a..becf658956d 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -33155,7 +33155,7 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
// Only do this on the last DAG combine as it can interfere with other
// combines.
- if (!DCI.isAfterLegalizeVectorOps())
+ if (!DCI.isAfterLegalizeDAG())
return SDValue();
// Try to improve a sequence of srl (and X, C1), C2 by inverting the order.
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