diff options
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 7 |
2 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp index 695e0f6326d..309430b0e9c 100644 --- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -103,8 +103,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_ICMP, 1, Ty}, Legal); if (!ST.useSoftFloat() && ST.hasVFP2()) { - setAction({G_FADD, s32}, Legal); - setAction({G_FADD, s64}, Legal); + for (unsigned BinOp : {G_FADD, G_FSUB}) + for (auto Ty : {s32, s64}) + setAction({BinOp, Ty}, Legal); setAction({G_LOAD, s64}, Legal); setAction({G_STORE, s64}, Legal); @@ -113,8 +114,9 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) { setAction({G_FCMP, 1, s32}, Legal); setAction({G_FCMP, 1, s64}, Legal); } else { - for (auto Ty : {s32, s64}) - setAction({G_FADD, Ty}, Libcall); + for (unsigned BinOp : {G_FADD, G_FSUB}) + for (auto Ty : {s32, s64}) + setAction({BinOp, Ty}, Libcall); setAction({G_FCMP, s1}, Legal); setAction({G_FCMP, 1, s32}, Custom); diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index c01cc064e1a..99155103090 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -242,11 +242,10 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { : &ARM::ValueMappings[ARM::GPR3OpsIdx]; break; } - case G_FADD: { + case G_FADD: + case G_FSUB: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); - assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) && - "Unsupported size for G_FADD"); - OperandsMapping = Ty.getSizeInBits() == 64 + OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] : &ARM::ValueMappings[ARM::SPR3OpsIdx]; break; |
