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Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp7
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
index c01cc064e1a..99155103090 100644
--- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
@@ -242,11 +242,10 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
: &ARM::ValueMappings[ARM::GPR3OpsIdx];
break;
}
- case G_FADD: {
+ case G_FADD:
+ case G_FSUB: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
- assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) &&
- "Unsupported size for G_FADD");
- OperandsMapping = Ty.getSizeInBits() == 64
+ OperandsMapping =Ty.getSizeInBits() == 64
? &ARM::ValueMappings[ARM::DPR3OpsIdx]
: &ARM::ValueMappings[ARM::SPR3OpsIdx];
break;
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