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| author | Javed Absar <javed.absar@arm.com> | 2017-10-30 13:51:56 +0000 |
|---|---|---|
| committer | Javed Absar <javed.absar@arm.com> | 2017-10-30 13:51:56 +0000 |
| commit | 5cde1ccb2998fe06e3930c1d5a8f3c4fb93e845d (patch) | |
| tree | bb084cd53a3650fc362f8a8c2fc6832faf7968ca /llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | |
| parent | 404fcd3069def112f95822bbd48e6e3e2b27f0df (diff) | |
| download | bcm5719-llvm-5cde1ccb2998fe06e3930c1d5a8f3c4fb93e845d.tar.gz bcm5719-llvm-5cde1ccb2998fe06e3930c1d5a8f3c4fb93e845d.zip | |
[GlobalISel|ARM] : Allow legalizing G_FSUB
Adding support for VSUB.
Reviewed by: @rovka
Differential Revision: https://reviews.llvm.org/D39261
llvm-svn: 316902
Diffstat (limited to 'llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index c01cc064e1a..99155103090 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -242,11 +242,10 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { : &ARM::ValueMappings[ARM::GPR3OpsIdx]; break; } - case G_FADD: { + case G_FADD: + case G_FSUB: { LLT Ty = MRI.getType(MI.getOperand(0).getReg()); - assert((Ty.getSizeInBits() == 32 || Ty.getSizeInBits() == 64) && - "Unsupported size for G_FADD"); - OperandsMapping = Ty.getSizeInBits() == 64 + OperandsMapping =Ty.getSizeInBits() == 64 ? &ARM::ValueMappings[ARM::DPR3OpsIdx] : &ARM::ValueMappings[ARM::SPR3OpsIdx]; break; |
